Reference-Less Frequency Detector for One-Cycle Threshold Sensing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional frequency detectors require a reference clock, which is not available in all applications, and are slow in comparison, especially in memory interfaces where fast detection beyond a frequency threshold is necessary.

Innovation Solution

A fast-response reference-less frequency detector is implemented using two pulse-shaping circuits in series, which modify the input clock signal to generate an intermediate signal and a control signal, allowing frequency detection without an external reference clock, capable of producing a result within one cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional frequency detection methods using separate counters are used, then frequency comparison can be performed, but the detection speed is slow and requires a reference clock

Engineering Contradiction:
Improvedetection speedVSAvoidcircuit complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent combines the frequency detection and threshold comparison functions into a single integrated circuit that processes the input clock signal directly. The circuit merges the counter functionality with the comparison logic, eliminating the need for separate counters and reference clock infrastructure, thereby achieving fast detection without increasing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the reference clock requirement from the detection system by implementing a reference-less detection mechanism. The circuit takes out the external reference clock dependency and replaces it with an internal threshold-based comparison mechanism that operates directly on the input clock signal, enabling fast detection in applications where reference clocks are unavailable

Inventive Principle:
Principle #2Taking out (Extraction)

2Adaptability or versatility

If conventional frequency detectors requiring reference clock are used, then frequency comparison is possible, but they cannot operate in applications without reference clock

Engineering Contradiction:
Improveapplication adaptabilityVSAvoiddetection accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent creates a universal frequency detection circuit that can operate in multiple application scenarios - both where reference clocks are available and where they are not. The circuit maintains detection accuracy by implementing a threshold-based comparison mechanism that provides reliable frequency detection across different operating conditions, thereby achieving high adaptability without sacrificing reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of time

If fast frequency detection within one cycle is implemented, then detection speed improves, but conventional methods cannot achieve this without reference clock

Engineering Contradiction:
Improvedetection timeVSAvoidcircuit structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-configuring the circuit with threshold values that enable immediate frequency detection upon receiving the input clock signal. The circuit is prepared in advance with the necessary comparison parameters, allowing it to perform fast one-cycle detection without needing to acquire a reference clock first, thereby reducing detection time without excessive circuit complexity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10135431B2Fast-response reference-less frequency detector
Publication Date: 2018.11.20 INTEGRATED DEVICE TECH INC
  • US10135431B2 patent drawing
  • US10135431B2 patent drawing
  • US10135431B2 patent drawing

AI summary

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.