Reference-Locked Ring Oscillator for Fast Clock Settling
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Solution Overview
Problem
Phase Locked Loops (PLLs) face bandwidth limitations, leading to slow frequency settling times, particularly in high-frequency clocking applications like radio communications, where precision and stability are critical.
Innovation Solution
A ring oscillator with a buffer chain is configured to operate in two modes: ring-oscillator-injection mode and ring-oscillator-closed-loop mode, using a reference gating circuit to selectively enable and disable buffer stages, allowing for faster frequency adjustments and improved precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional closed-loop PLL architecture is used, then the system provides stable frequency control, but the bandwidth limitations cause slow frequency settling times
Solution Approach 1:
The patent implements dynamic switching between two operational modes: injection mode for fast frequency acquisition and closed-loop mode for stable frequency control. The system transitions from a static architecture to a dynamic one that adapts its operating characteristics based on the required function, thereby resolving the contradiction between fast settling and stability.
Solution Approach 2:
The system employs periodic mode switching where the injection buffer is enabled during frequency transitions and disabled during stable operation. This periodic alternation between open-loop injection and closed-loop control allows the system to achieve both fast frequency settling and maintained stability at different operational phases.
2Measurement precision
If the reference clock continuously controls the ring oscillator, then phase alignment is maintained, but frequency adjustment speed is limited by the reference clock rate
Solution Approach 1:
The patent segments the control function into two independent pathways: a fast injection pathway that bypasses the reference clock for rapid frequency changes, and a precision reference pathway that maintains phase alignment. This segmentation allows simultaneous optimization of both speed and precision without mutual interference.
Solution Approach 2:
The injection buffer acts as an intermediary mechanism that temporarily decouples the ring oscillator from the reference clock during frequency transitions. This intermediary allows the oscillator to respond immediately to frequency commands while the reference clock continues to provide phase alignment precision when re-engaged.
Data Source
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Figure 2A~2C
Figure 3
AI summary
Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.