Reference Memory Cell Control Circuit for STT-RAM Data Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in accurately reading and correcting data from reference memory cells due to thermal instability and noise, leading to errors in stored data, particularly in STT-RAM and similar technologies.
Innovation Solution
The implementation of a semiconductor device with a reference control circuit that selectively connects reference memory cells to sense amplifiers, allowing for error detection and correction using ECC or comparison circuits, reducing the writing frequency to reference memory cells and improving their reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reference memory cells are frequently written to maintain data accuracy, then data reliability improves, but thermal instability and noise increase causing more errors
Solution Approach 1:
The patent applies preliminary action by pre-charging bitlines to a specific potential level before reading reference memory cells. This preparatory step ensures that when reference cells are accessed, the bitlines are already in the correct state to accurately detect the reference potential, reducing the need for frequent re-writes to maintain accuracy and thereby reducing thermal instability effects.
Solution Approach 2:
The patent implements feedback through a control circuit that monitors the state of reference memory cells and selectively connects them to sense amplifiers based on their reliability. When errors are detected or anticipated, the system adjusts the reading process by selecting different reference cells or adjusting read parameters, creating a feedback loop that maintains data accuracy without requiring frequent writes that would induce thermal instability.
2Measurement precision
If reference memory cells are selectively connected to sense amplifiers for error detection, then reading accuracy improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the reference memory cell array into multiple selectable groups, where each group can be independently connected to sense amplifiers. This segmentation allows the control circuit to selectively activate only the necessary reference cells for each read operation, improving reading accuracy through targeted measurement while keeping the control circuit complexity manageable by using simple switching mechanisms rather than complex control logic.
Solution Approach 2:
The patent implements universality by designing the control circuit to perform multiple functions: it selectively connects reference memory cells to sense amplifiers, monitors their states, and adjusts reading operations based on detected conditions. This multi-functional approach consolidates what could be multiple separate circuits into a single versatile control unit, improving reading accuracy without proportionally increasing device complexity.
3Reliability
If writing frequency to reference memory cells is reduced to improve reliability, then thermal instability effects decrease, but data accuracy may deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-charging bitlines to the appropriate potential level before reading reference memory cells. This preparatory step ensures accurate detection of reference potentials without requiring frequent re-writes to the reference cells themselves. By preparing the reading circuitry in advance, the system maintains data accuracy while minimizing write operations that would cause thermal instability.
Solution Approach 2:
The patent implements feedback through a control circuit that monitors reference cell states and adjusts subsequent read operations accordingly. When reference cells show signs of degradation or errors, the system can switch to alternative reference cells or adjust reading parameters, creating a feedback mechanism that maintains data accuracy without requiring frequent writes that would compromise reference cell stability.
Data Source
AI summary
A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier.