Reference Picture Caching for Video Memory Bandwidth Reduction
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Solution Overview
Problem
Existing video encoding and decoding technologies face inefficiencies in managing memory access and power consumption due to the lack of effective strategies for determining whether to store video pictures in dedicated chip memory or non-dedicated system memory, leading to suboptimal bandwidth and power usage.
Innovation Solution
The proposed techniques involve generating future reference picture lists to estimate the frequency of picture access as a reference for inter-prediction, allowing the video encoder or decoder to determine whether to store the current picture in dedicated chip memory or non-dedicated system memory based on these estimates, thereby optimizing memory usage and reducing power and bandwidth consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pictures are stored in dedicated chip memory, then access speed and power efficiency are improved, but memory capacity and cost are limited
Solution Approach 1:
The patent segments the memory system into two distinct parts: dedicated chip memory (fast, low-power, limited capacity) and system memory (slower, higher-power, larger capacity). By dividing the storage function across these two segments, the system can store frequently accessed reference pictures in the fast chip memory while maintaining overall large storage capacity through system memory, thus resolving the contradiction between access speed and memory capacity.
Solution Approach 2:
The patent applies local quality by assigning different storage locations based on access patterns. Reference pictures that are frequently needed for inter-prediction are placed in the dedicated chip memory with high-speed access characteristics, while less frequently accessed pictures are stored in system memory. This localized optimization of storage quality based on specific access requirements resolves the contradiction by providing fast access where needed while maintaining overall system capacity.
2Use of energy by moving object
If pictures are stored in dedicated chip memory, then power consumption is reduced, but memory availability and flexibility are constrained
Solution Approach 1:
The patent implements a dynamic memory management system where the decision to store pictures in chip memory or system memory is not fixed but adapts based on predicted future reference patterns. The system generates future reference picture lists and uses this information to dynamically determine which pictures should be cached in chip memory, allowing the memory allocation to be flexible and adaptive rather than static, thus resolving the contradiction between power efficiency and memory availability.
Solution Approach 2:
The patent applies preliminary action by generating future reference picture lists in advance and using this predictive information to proactively decide which pictures to store in chip memory before they are actually needed. This advance planning allows the system to optimize power consumption by pre-positioning frequently accessed pictures in low-power memory while maintaining the flexibility to adapt to different future reference patterns, resolving the contradiction between power efficiency and adaptability.
3Loss of energy
If future reference picture lists are generated to optimize memory storage, then power and bandwidth consumption are reduced, but computational complexity increases
Solution Approach 1:
The patent implements feedback by using the generated future reference picture lists to inform memory storage decisions. The system creates predictive models of future reference patterns, uses this information to optimize current memory allocation, and thereby reduces future bandwidth and power consumption. This feedback loop allows the system to make intelligent storage decisions that balance the computational cost of generating future reference lists against the energy savings from optimized memory access patterns.
Data Source
AI summary
A method includes generating a plurality of future reference picture lists associated with a plurality of future pictures of a set of pictures, wherein the set of pictures includes a current picture and the plurality of future pictures, and the plurality of future pictures follow the current picture in coding order, determining, based on information derived from the plurality of future reference picture lists associated with the plurality of future pictures, whether to write the current picture in a dedicated chip memory or whether to write the current picture in a non-dedicated system memory, and writing the current picture in the dedicated chip memory or the non-dedicated system memory based on the determination of whether to write the current picture in the dedicated chip memory or whether to write the current picture the non-dedicated system memory.