Reference-Sampling Fractional-N PLL Without Buffer or Charge Pump
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Solution Overview
Problem
Type-I fractional-N Phase Locked Loops (PLLs) face challenges with high power consumption and noise due to the reference clock buffer and charge-pump contributions, which degrade the figure-of-merit (FOM) and make fractional frequency multiplication complex, while traditional Type-II PLLs have higher noise and power consumption.
Innovation Solution
A reference sampling Type-I fractional-N PLL that directly samples the reference clock, eliminating the reference buffer and using a passive sampling switch and switched-capacitor voltage interpolator to achieve fractional-N output, reducing power consumption and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a reference buffer and charge-pump are used in Type-I fractional-N PLL, then the PLL can achieve frequency multiplication, but power consumption and noise increase
Solution Approach 1:
The patent extracts and removes the reference buffer and charge-pump components from the Type-I fractional-N PLL architecture. By eliminating these noisy and power-consuming components, the invention achieves frequency multiplication through an alternative mechanism (direct sampling of reference clock by the divider) that does not require these traditional elements, thereby simultaneously reducing both power consumption and noise.
2Device complexity
If Type-II PLL architecture is used, then the design is simpler, but noise and power consumption are higher
Solution Approach 1:
The patent inverts the traditional PLL architecture by making the divider directly sample the reference clock without requiring a reference buffer, and by eliminating the charge-pump entirely. This inversion of the conventional Type-II architecture allows the system to achieve Type-I PLL performance (lower noise and power) while maintaining design simplicity through the direct sampling approach.
3Object-generated harmful factors
If Type-I PLL bandwidth is increased to suppress VCO noise, then noise suppression improves, but reference buffer and charge-pump power consumption increases
Solution Approach 1:
The patent removes the reference buffer and charge-pump components that are responsible for power consumption in Type-I PLLs. By eliminating these components while maintaining the high bandwidth architecture, the invention achieves noise suppression without the associated power penalty, as the high bandwidth is maintained through the direct sampling path rather than through power-intensive buffering and charging circuits.
Data Source
AI summary
A reference sampling Type-I fractional-N PLL directly samples the reference clock and therefore does not use a reference buffer. Here, a phase-detector is a passive sampling switch which neither consumes any power nor generates any noise. Therefore, all the major contributors of in-band phase-noise are eliminated by the reference sampling Type-I fractional-N divider. A double sampling phase-detector with a switched-capacitor passive voltage interpolator circuit is used to achieve fractional-N output. To achieve a high resolution of the voltage interpolator or the switched capacitor, a sigma-delta modulator is used.