Reference Voltage Circuit With PMOS Back-Gate Adjustment
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Solution Overview
Problem
Conventional reference voltage circuits struggle to maintain stable constant voltage operation at low power supply voltages, particularly when the voltage based on a PN junction element changes due to external temperature variations.
Innovation Solution
The proposed reference voltage circuit includes a differential amplifier circuit with a voltage adjustment circuit that adjusts the voltage between the common source and common back gate of PMOS transistors, ensuring stable saturation operation even at low power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage circuit uses a conventional differential amplifier circuit with PMOS and NMOS transistors, then the circuit can perform differential amplification, but the MOS transistors cannot operate in saturation at low power supply voltages (2V or less) when input voltage changes due to temperature variations
Solution Approach 1:
The patent introduces a voltage adjustment circuit as an intermediary component between the power supply and the differential amplifier circuit. This circuit adjusts the power supply voltage based on temperature-dependent input voltage changes, ensuring that the voltage difference between source and back gate of PMOS transistors remains sufficient for saturation operation. The voltage adjustment circuit acts as a mediator that compensates for temperature effects without requiring changes to the core differential amplifier structure.
Solution Approach 2:
The patent dynamically changes the power supply voltage parameter to the differential amplifier circuit based on temperature conditions. By adjusting the power supply voltage in response to input voltage changes caused by temperature variations, the circuit maintains the necessary voltage headroom for MOS transistor saturation operation. This parameter adjustment ensures that the drain-source voltage of PMOS transistors remains above the threshold required for saturation even at low overall power supply voltages.
2Use of energy by moving object
If the power supply voltage is reduced to achieve low voltage operation, then energy consumption is reduced, but the MOS transistors cannot maintain saturation operation when input voltage varies with temperature
Solution Approach 1:
The voltage adjustment circuit operates autonomously to monitor and compensate for temperature-induced voltage variations. It automatically adjusts the power supply voltage to the differential amplifier circuit based on the state of the input voltage, without requiring external intervention. This self-service mechanism ensures that the circuit maintains saturation operation stability while operating at low power supply voltages, effectively managing its own voltage requirements in response to environmental changes.
3Reliability
If the voltage adjustment circuit adjusts the power supply voltage based on input voltage changes, then MOS transistor saturation operation is maintained, but the circuit complexity increases
Solution Approach 1:
The voltage adjustment circuit is designed to perform multiple functions: it monitors input voltage changes, determines temperature-dependent voltage variations, and adjusts the power supply voltage accordingly. By consolidating these functions into a single circuit block, the patent minimizes the increase in overall circuit complexity while achieving reliable saturation operation. The circuit can be implemented using standard CMOS processes and integrates well with the differential amplifier structure.
Data Source
AI summary
A reference voltage circuit includes a differential amplifier circuit capable of stably operating at a constant voltage even if a collector voltage of an NPN transistor changes with temperature and is received. A voltage adjustment circuit is included between commonly connected sources and commonly connected back gates of a first PMOS transistor and a second PMOS transistor serving as input ports of a differential amplifier circuit. A voltage generated by the voltage adjustment circuit is configured to adjust a source-back gate voltage of the first PMOS transistor and the second PMOS transistor in accordance with a voltage change in which the collector voltage of the NPN transistor received at one of the input ports of the differential amplifier circuit.