Reference Voltage Training for Semiconductor Signal Buffers
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Solution Overview
Problem
The power consumption of semiconductor devices in mobile systems is high, affecting the weight and performance of portable devices, and existing designs do not efficiently manage command and address signals to optimize data transmission speeds.
Innovation Solution
A semiconductor device and system that includes a flag signal generator, reference voltage generator, and buffers to generate and regulate signals, allowing for efficient data transmission and calibration, enabling the verification of valid windows for improved operation speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If power consumption is reduced to decrease mobile system weight, then battery capacity can be reduced, but data transmission speeds may be compromised
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the reference voltage level based on the command type. During training operations, a first reference voltage level is used, while during normal operations, a second reference voltage level is used. This allows the device to optimize power consumption and speed by changing the voltage parameter according to operational requirements, enabling lighter battery capacity while maintaining adequate data transmission speeds.
2Device complexity
If command signals and address signals are received through ten pins simultaneously, then device complexity is reduced, but signal decoding complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the combined command and address signals into separate components through dedicated decoding circuits. The command decoder extracts command signals while the address decoder extracts address signals from the multiplexed input, allowing the system to maintain simplified pin structure while managing decoding complexity through functional separation.
Solution Approach 2:
The patent introduces intermediary decoding circuits that act as mediators between the combined signal input and the separate command/address signal processing paths. These decoders translate the multiplexed signals into separated control signals, enabling the system to benefit from reduced pin count while maintaining manageable decoding complexity through intermediate processing stages.
3Device complexity
If reference voltage level is fixed, then circuit design is simplified, but training operation accuracy is reduced
Solution Approach 1:
The patent applies dynamics by making the reference voltage level changeable based on operational mode. The reference voltage generator switches between a first reference voltage level during training operations and a second reference voltage level during normal operations. This dynamic adjustment improves measurement precision during training while keeping the overall circuit design relatively simple through controlled variability.
Data Source
AI summary
The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. The reference voltage generator receives a set code in response to the flag signal, and generates a reference voltage having a voltage level regulated according to the set code. The first buffer buffers the external signal in response to the reference voltage to generate an internal signal, and generates a calibration code in response to the flag signal.