Reference Voltage Circuit Low Power Supply Rejection Ratio
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Solution Overview
Problem
Conventional reference voltage circuits face challenges in maintaining a high power supply rejection ratio, especially when the power supply voltage is low, due to the channel length modulation effect of depletion NMOS transistors, which affects the stability of the reference voltage.
Innovation Solution
A reference voltage circuit is designed with a differential amplifier circuit and a control transistor to maintain a constant internal power supply voltage, using a depletion type transistor and an enhancement type transistor, ensuring the depletion transistor operates in saturation, and a junction type transistor with a resistor, to enhance the power supply rejection ratio by adjusting the control transistor based on input offset voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cascode circuit is added to the power supply terminal to improve power supply rejection ratio, then the reference voltage stability improves, but the device complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the differential amplifier circuit continuously monitors the internal power supply voltage and adjusts the control transistor's gate voltage accordingly. This closed-loop feedback system maintains the internal power supply voltage at a constant level, thereby improving the power supply rejection ratio without requiring complex cascode circuits.
Solution Approach 2:
The control transistor automatically adjusts its operation based on the feedback from the differential amplifier to maintain constant internal power supply voltage. The circuit self-regulates by using the voltage difference detected by the differential amplifier to control the power supply voltage, eliminating the need for external complex stabilization circuits.
2Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then energy efficiency improves, but the power supply rejection ratio deteriorates due to channel length modulation effect
Solution Approach 1:
The patent changes the operating parameters of the control transistor by using the differential amplifier to precisely control the gate voltage. This allows the transistor to operate in the saturation region even at low power supply voltages, maintaining a high power supply rejection ratio while enabling low power consumption operation.
Solution Approach 2:
The feedback mechanism ensures that the internal power supply voltage remains constant regardless of the external power supply voltage level. This allows the circuit to maintain high power supply rejection ratio even when operating at low power consumption levels, as the feedback continuously compensates for voltage variations.
Data Source
AI summary
Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal (10) becomes lower and thus an NMOS transistor (71) operates in non-saturation to reduce an output resistance (ro71) of the NMOS transistor (71), when a gain (Ao) of a differential amplifier circuit (60) is large, the power supply rejection ratio (PSRRLF) is also large. Therefore, even when a minimum operating voltage of the reference voltage circuit is low, the power supply rejection ratio (PSRRLF) can be made larger. In other words, since the gain (Ao) of the differential amplifier circuit (60) contributes to the power supply rejection ratio (PSRRLF), when the gain (Ao) of the differential amplifier circuit (60) increases, the power supply rejection ratio (PSRRLF) also becomes larger by the increase.