Closed-Loop Reference Voltage Tuning for Data Recovery Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed source synchronous digital data communication systems face challenges in accurately generating and tuning a reference voltage (Vref) due to variable skew between clock and data signals, leading to increased bit error rates (BER) despite existing calibration methods like PVT shmooing, which may result in sub-optimal settings for certain parts.
Innovation Solution
A data recovery circuit that includes a comparator, sampler, summing circuit, counter, and reference voltage generator, which adjusts the Vref by evaluating the average voltage difference between data input signals and using a closed-loop system to fine-tune the voltage, ensuring it is optimal for both coarse and fine training modes, thereby reducing BER.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PVT shmooing is used to calibrate Vref, then a fixed value can be set for all parts, but the fixed value may be sub-optimal for certain parts and increase bit error rate
Solution Approach 1:
The patent implements a dynamic Vref calibration system that transitions from a static fixed value approach to an adaptive system. The calibration circuit continuously monitors data quality metrics (such as eye diagram parameters or bit error rate) and automatically adjusts Vref to optimal values in real-time, allowing the system to adapt to manufacturing variations and operating conditions without requiring manual recalibration for each part.
Solution Approach 2:
The patent employs feedback mechanisms where the calibration circuit receives feedback signals indicating data quality or error rates, and uses this feedback to iteratively adjust Vref. The system compares the current Vref performance against target thresholds and modifies the reference voltage accordingly, creating a closed-loop control system that optimizes data recovery accuracy while simplifying the manufacturing calibration process.
2Ease of manufacture
If Vref is set to a fixed value for all parts, then manufacturing is simplified, but the value may be sub-optimal for certain parts processed within acceptable manufacturing tolerances
Solution Approach 1:
The patent implements a self-calibrating Vref system where the calibration circuit automatically determines optimal reference voltage values without requiring external intervention or manual adjustment for each part. The system uses built-in monitoring of data quality metrics and self-adjusts Vref to optimal settings, enabling high-precision voltage calibration while maintaining simplified production processes. This self-service approach eliminates the need for complex manual calibration procedures while achieving part-specific optimization.
3Reliability
If the clock signal is delayed or data signal is delayed to achieve alignment, then clock and data alignment is improved, but the system complexity increases
Solution Approach 1:
The patent implements a multi-functional calibration circuit that simultaneously performs both clock alignment and Vref optimization functions. Rather than requiring separate independent circuits for timing adjustment and voltage calibration, the unified calibration system integrates multiple functions into a single modular block, reducing overall system complexity while achieving both signal alignment and optimal reference voltage settings for improved data recovery accuracy.
Data Source
AI summary
A data recovery circuit includes a comparator for providing a comparator output signal in response to a difference in voltage between a data input signal and the reference voltage, a sampling circuit for sampling the comparator output signal to provide a sample signal, a summing circuit for providing an up signal in response to an average of logic high values of the sample signal exceeding logic low values of the input samples signal, and a down signal in response to an average of the low logic values of the sample signal exceeding the logic high values of the sample signal, a counter for counting up in response to activations of the up signal and counting down in response to activations of the down signal to provide a count signal, and a reference voltage generator for generating the reference voltage in response to the count signal.