Reference Voltage Switching in Two-Step Flash ADCs
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Solution Overview
Problem
Two-step flash converters face limitations in bandwidth due to settling time and cycle-dependent settling errors, which are exacerbated by parasitic capacitance and level shifters, leading to inefficiencies in reference voltage switching and comparison processes.
Innovation Solution
A reference voltage control circuit that selectively switches between two reference voltages using switches controlled by the zero crossing comparator, ensuring that the reference voltages settle before being used by the flash converter, and utilizing level shifters only during non-critical edges to minimize delays and errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If reference voltage switching is performed quickly to improve bandwidth, then conversion speed increases, but settling errors increase due to insufficient settling time
Solution Approach 1:
The patent applies preliminary action by pre-charging the reference voltage nodes before switching occurs. The circuit maintains reference voltages on both sides of switches in advance, so when switching happens, the voltages are already settled and ready, eliminating settling errors while enabling fast switching for high bandwidth operation
Solution Approach 2:
The patent uses beforehand cushioning by implementing a pre-charge mechanism that prepares the reference voltage nodes before the actual switching event. This cushioning charge ensures that when the switch transitions, there is no voltage transient or settling error, allowing rapid switching without precision degradation
2Measurement precision
If parasitic capacitance and level shifters are minimized to reduce settling errors, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent merges the pre-charge function with the reference voltage generation circuitry itself. By integrating the pre-charge capacitors and switches into the existing reference voltage distribution network, the design achieves settling error elimination without adding separate complex pre-charge circuits, thus maintaining relatively simple device architecture
Solution Approach 2:
The reference voltage distribution circuit serves multiple functions: it generates reference voltages, distributes them to comparators, and simultaneously performs pre-charging of switch nodes. This multi-functionality eliminates the need for dedicated pre-charge circuits, reducing overall device complexity while maintaining high measurement precision
3Productivity
If reference voltages are switched simultaneously to both reference nodes, then switching efficiency improves, but voltage instability occurs during transition
Solution Approach 1:
The patent applies preliminary action by ensuring both reference nodes are pre-charged to their target voltages before the switching event. This advance preparation allows simultaneous switching to occur without voltage transients or instability, maintaining both switching efficiency and voltage stability
Solution Approach 2:
The patent uses pre-charge capacitors as intermediary energy storage elements that decouple the switching action from voltage transitions. These capacitors act as mediators that can rapidly transfer charge without causing voltage instability, enabling efficient simultaneous switching while maintaining stable reference voltages throughout the transition
Data Source
AI summary
A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.