Reference Voltage Generator Circuit Using Inverted P-Channel MOS Transistors
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Solution Overview
Problem
Existing reference voltage generators face challenges in maintaining a reference voltage close to the supply voltage level, especially at low supply voltages, leading to insufficient dynamic range and high power consumption due to the need for external capacitors and inefficient current handling.
Innovation Solution
A fully integrable reference voltage generator circuit using MOS transistors with a capacitive element to adjust the conduction of a third transistor based on output voltage variations, eliminating the need for external capacitors and optimizing current consumption according to downstream circuit requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a classic follower circuit with N-channel MOS transistor is used to generate reference voltage, then the circuit structure is simple, but the reference voltage level cannot be maintained close to the supply voltage at low supply voltages due to gate-source voltage requirements
Solution Approach 1:
The patent inverts the conventional follower circuit structure by using a P-channel MOS transistor instead of an N-channel transistor, and by switching the current source connection from ground to the positive supply voltage. This inversion allows the reference voltage to be maintained close to the supply voltage level even at low supply voltages, resolving the contradiction between simple structure and voltage level stability.
2Reliability
If the follower structure is inverted to bring VrefP closer to Vdd, then the reference voltage level improves, but the transistor must be sized for worst-case current which increases power consumption
Solution Approach 1:
The patent introduces a dynamic current sharing mechanism where a second P-channel MOS transistor and its associated current source are activated only when the downstream converter draws current. This dynamic operation allows the first transistor to be sized for normal operation rather than worst-case scenarios, reducing power consumption while maintaining reference voltage stability.
Solution Approach 2:
The circuit automatically adjusts current distribution between the two parallel transistor branches based on load conditions. When current is drawn from the reference voltage, the circuit self-regulates by activating the second transistor through the current mirror mechanism, eliminating the need for external control while optimizing power consumption.
3Stability of the object's composition
If external capacitors are used to stabilize reference voltage levels, then voltage stability improves, but the device complexity and integration difficulty increase
Solution Approach 1:
The patent merges the voltage stabilization function directly into the follower circuit structure by using the intrinsic capacitance of the MOS transistors and the feedback mechanism. This eliminates the need for separate external capacitors, reducing device complexity and improving integrability while maintaining voltage stability through the circuit's inherent feedback control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable and efficient reference voltage generation with reduced power consumption and no external capacitors, suitable for both differential and non-differential modes, enhancing the dynamic range and integration of the circuit.
Implementation Method 1
a capacitive element directly connecting said output terminal to a conduction terminal of the third transistor to vary the conduction of this third transistor in the event of variation of the output voltage
Data Source
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Figure 7
AI summary
The circuit has a current source (31) connecting a supply voltage terminal (2) to a gate of a P channel MOS transistor (MP0). Another current source (22) connects a drain of a P channel MOS transistor (MP1) to a ground (3). N channel MOS transistor (MN0) connects the current sources together. A capacitor (Cbyp) is provided between an output terminal (13) and a source of the transistor (MN0) for varying the potential in the source of the transistor (MN0) in case of variation of potential in the output terminal.