Reference Voltage Generator Integrated With Memory Array Lines
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Solution Overview
Problem
Conventional reference-voltage-generators occupy significant semiconductor real estate and require complex fabrication processes, limiting their packing density and increasing costs.
Innovation Solution
Integrating resistive units that match the sense/access lines of memory arrays, allowing for simultaneous fabrication and patterning with memory components, thereby reducing footprint and fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional reference-voltage-generators are used, then reference voltage generation is achieved, but semiconductor real estate is significantly occupied and fabrication complexity increases
Solution Approach 1:
The patent merges the reference-voltage-generator fabrication process with the memory array fabrication process. The resistive units are formed simultaneously with the sense/access lines using the same deposition and patterning steps, eliminating the need for separate reference-voltage-generator fabrication processes and reducing overall device complexity
Solution Approach 2:
The sense/access lines of the memory array serve dual purposes: they function as memory access lines and simultaneously serve as resistive units for reference voltage generation. This multi-functionality eliminates dedicated reference voltage structures, reducing semiconductor real estate occupation
2Area of stationary object
If conventional reference-voltage-generators are used, then reference voltage generation is achieved, but packing density is limited
Solution Approach 1:
By combining the reference-voltage-generator functionality with the memory array structures, the patent eliminates separate reference voltage generation circuits. The resistive units are formed from the same conductive interconnect structures that serve as sense/access lines, thereby conserving semiconductor space and increasing packing density
Solution Approach 2:
The sense/access lines perform dual functions as both memory access pathways and reference voltage generating elements. This eliminates the need for additional dedicated reference voltage structures, allowing more memory cells to be packed into the same semiconductor area
3Ease of manufacture
If separate fabrication processes are used for reference-voltage-generators, then reference voltage generation is achieved, but fabrication complexity and costs increase
Solution Approach 1:
The patent combines the fabrication of reference-voltage-generators with the memory array fabrication into a single integrated process. The resistive units are formed using the same conductive interconnect deposition and patterning steps as the sense/access lines, eliminating separate fabrication processes and reducing overall fabrication complexity
Solution Approach 2:
The resistive units are formed during the initial conductive interconnect fabrication steps, before the memory array structures are fully completed. This preliminary formation of resistive units allows them to be created as part of the standard fabrication sequence without requiring additional processing steps
Data Source
AI summary
Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.