Differential Reference Voltage Generator PSRR Optimization
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Solution Overview
Problem
Existing reference generators in analog-to-digital converters (ADCs) face performance degradation due to errors in reference voltage, leading to reduced Signal-to-Noise Ratio (SNR) and Equivalent Number of Bits (ENOB), exacerbated by insufficient settling error and supply noise disturbance, which can be mitigated but at the cost of increased die size and circuit complexity.
Innovation Solution
A differential reference voltage generator using open-loop source follower transistors biased by a replica-bias circuit with a voltage drop circuit, implemented on-chip to achieve high power supply rejection ratio (PSRR) and fast settling behavior, while minimizing signal transfer from the supply to the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large decoupling capacitors are used to improve power supply rejection ratio, then PSRR is improved, but die size increases
Solution Approach 1:
The patent changes the operating parameters of the reference generator circuit by introducing voltage offsets to different supply nodes, transforming the approach from passive filtering (capacitors) to active parameter control. This allows achieving high PSRR through circuit operation parameters rather than large physical components.
Solution Approach 2:
The patent extracts the noise rejection function from the traditional capacitor-based filtering approach and implements it through a dedicated offset circuit that actively compensates for supply noise. This separates the PSRR function from the reference voltage generation function, allowing optimization of each independently without requiring large decoupling capacitors.
2Reliability
If off-chip capacitors are used to improve power supply rejection, then PSRR is improved, but pin count and circuit complexity increase
Solution Approach 1:
The patent merges the power supply rejection function with the on-chip reference generator circuit by integrating an offset circuit that directly interfaces with the reference generation transistors. This consolidation eliminates the need for separate off-chip decoupling capacitors and their associated pins, reducing overall system complexity while maintaining PSRR performance.
Solution Approach 2:
The offset circuit acts as an intermediary between the power supply and the reference voltage generation circuit. It mediates the supply noise by providing compensating voltage offsets to the transistor supply nodes, thereby rejecting power supply disturbances without requiring external passive components.
3Device complexity
If conventional reference generator is used, then circuit simplicity is maintained, but settling error increases after switching glitches
Solution Approach 1:
The offset circuit performs preliminary action by continuously providing voltage offsets that preemptively counteract the effects of supply noise and switching glitches. This proactive compensation ensures that the reference voltage remains stable and settles quickly after disturbances, improving transient response without complicating the overall circuit architecture.
Data Source
AI summary
In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.