Reference Voltage Generator Symmetric Layout for Chip Size Reduction
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Solution Overview
Problem
Conventional reference voltage trimming circuits for semiconductor devices face challenges due to the large number of lines required, leading to a bottleneck and increased chip size, which complicates the fabrication process and accuracy of device models.
Innovation Solution
A reference voltage generator with a voltage division unit and symmetrically arranged reference voltage output units that divide and trim external voltages, reducing the number of lines by halving the channels in a horizontal direction and vertically arranging lines to minimize the occupied region, thereby preventing bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional reference voltage trimming circuit is designed with sufficient trimming capability, then the voltage accuracy is improved, but the number of lines increases leading to chip size expansion and bottlenecks
Solution Approach 1:
The trimming circuit is divided into multiple independent trimming units, each handling a portion of the voltage trimming task. This segmentation allows the circuit to achieve comprehensive trimming capability while reducing the line density in any single region, thus preventing bottlenecks and reducing overall chip size.
Solution Approach 2:
The patent rearranges the trimming units and lines in a two-dimensional layout optimized for space utilization. By strategically positioning trimming units and routing lines across different regions of the chip, the design reduces line congestion and minimizes the occupied area while maintaining full trimming functionality.
2Adaptability or versatility
If more lines are formed in a limited space to increase trimming capability, then the voltage adjustment range is improved, but line bottlenecks occur complicating fabrication
Solution Approach 1:
The circuit is segmented into multiple trimming units distributed across the chip, each with its own set of lines. This distribution prevents line bottlenecks by spreading out the connections, making the fabrication process easier while maintaining a wide voltage adjustment range through the combined capability of all trimming units.
Solution Approach 2:
Instead of providing all trimming lines passing through a single bottleneck region, the patent implements partial trimming actions across multiple distributed units. Each unit handles a subset of the trimming function, collectively achieving the full adjustment range without requiring excessive lines in any one location, thereby simplifying fabrication.
3Device complexity
If a conventional trimming circuit layout is used, then the design is simple, but the occupied region is large and bottlenecks occur
Solution Approach 1:
The patent employs a optimized two-dimensional layout arrangement of trimming units and lines that maximizes space utilization. By carefully planning the spatial distribution and routing in the chip layout, the design achieves compact occupation of region while maintaining design simplicity through systematic arrangement patterns.
Solution Approach 2:
Multiple trimming units are merged into a unified circuit architecture with shared components and coordinated control. This merging reduces the total occupied region by eliminating redundant elements and optimizing the shared resources, while the systematic integration keeps the design manageable and relatively simple.
Data Source
AI summary
A reference voltage generator may include a voltage division unit configured to receive an external voltage, and divide the external voltage into a plurality of divided voltages. The reference voltage generator may include reference voltage output units configured to trim the divided voltages received from the voltage division unit according to a division control signal, and output supply reference voltages. The reference voltage output units may be symmetrically arranged at both sides of the voltage division unit.