Reference Voltage Mixing for High-Speed Memory Noise Immunity

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Solution Overview

Problem

High-speed integrated circuit memories like GDDR7 are susceptible to environmental noise due to their high sensitivity, which can lead to data transmission failures despite the small voltage swing between logic states.

Innovation Solution

The implementation of reference voltage (VREF) mixing, which combines power supply noise from both ends of the transmission line into a reference voltage used for data transmission and reception, is proposed to reduce sensitivity to environmental noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed data transmission is implemented in integrated circuit memories, then memory bandwidth and operating speed are improved, but sensitivity to environmental noise increases leading to data transmission failures

Engineering Contradiction:
Improvememory operating speedVSAvoiddata transmission reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent converts the harmful power supply noise into a beneficial reference voltage by mixing noise from both ends of the transmission line. The mixed reference voltage (VREF_MIX) incorporates noise components from both transmitting and receiving ends, which compensates for noise-induced voltage shifts and improves reception robustness at high speeds.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces a mixed reference voltage as an intermediary between the power supply noise and the data reception process. This intermediary voltage serves as a dynamic reference that adapts to noise conditions, enabling reliable data reception despite environmental interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If small voltage swing between logic states is used to increase data transmission rate, then bandwidth is improved, but sensitivity to noise increases causing reception errors

Engineering Contradiction:
Improvedata transmission rateVSAvoidnoise sensitivity
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent transforms the harmful effect of small voltage swings being susceptible to noise into a benefit by using the same noise to adjust the reference voltage. The mixed reference voltage dynamically adapts to the noise environment, maintaining accurate logic state detection despite small voltage margins.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Device complexity

If traditional reference voltage is used without noise mixing, then device complexity is low, but reception errors occur due to environmental noise

Engineering Contradiction:
Improvereference voltage circuit complexityVSAvoiddata reception accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the reference voltage generation into two independent parts: a traditional reference voltage generator and a noise mixing circuit. This segmentation allows the noise mixing function to be added modularly without completely redesigning the reference voltage generation system, thereby limiting complexity increase while improving reliability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12288581B2Efficient and low power reference voltage mixing
Publication Date: 2025.04.29 ADVANCED MICRO DEVICES INC
  • US12288581B2 patent drawing
  • US12288581B2 patent drawing
  • US12288581B2 patent drawing

AI summary

A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.