Reference Voltage Circuit With PMOS Back-Gate Adjustment
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Solution Overview
Problem
Conventional reference voltage circuits face challenges in maintaining stable operation at low power supply voltages, particularly when external temperature changes affect the voltage received at the differential amplifier circuit, leading to non-saturation conditions in MOS transistors.
Innovation Solution
A reference voltage circuit with a differential amplifier circuit that includes a voltage adjustment circuit to stabilize MOS transistor operation in saturation by adjusting the voltage between the common source and back gate of PMOS transistors, using a variable resistor or current source to counteract temperature-induced voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the voltage applied to the gate of the PMOS transistor decreases due to temperature change, then the source voltage decreases, but the drain-source voltage reduces causing the PMOS transistor to become unable to operate in saturation
Solution Approach 1:
The patent implements a feedback mechanism where the voltage applied to the gate of the PMOS transistor is dynamically adjusted based on temperature changes. The control circuit monitors temperature variations and modifies the gate voltage accordingly to maintain the drain-source voltage within the saturation region, preventing the transistor from exiting saturation despite temperature-induced voltage fluctuations.
Solution Approach 2:
The patent changes the operating parameters of the PMOS transistor by dynamically adjusting the gate voltage in response to temperature changes. This parameter adjustment ensures that the drain-source voltage remains sufficient to maintain saturation operation across varying temperature conditions, resolving the contradiction between temperature stability and saturation reliability.
2Temperature
If the voltage applied to the gate of the PMOS transistor increases, then the source voltage increases, but the drain-source voltage decreases leading to non-saturation operation
Solution Approach 1:
The feedback control circuit detects when the gate voltage becomes excessively high and adjusts it downward to prevent the drain-source voltage from dropping below the saturation threshold. This dynamic adjustment maintains the transistor in saturation region even when temperature changes would otherwise cause non-saturation operation.
Solution Approach 2:
The patent dynamically modifies the gate voltage parameter based on temperature conditions, ensuring that the drain-source voltage remains within the saturation region. This parameter control prevents both excessive voltage increases and decreases that would lead to non-saturation operation.
3Use of energy by moving object
If conventional differential amplifier circuit is used, then the circuit can operate at low power supply voltage, but MOS transistors cannot maintain saturation operation due to narrow voltage range
Solution Approach 1:
The patent introduces a feedback control mechanism that actively monitors and adjusts the gate voltage of the PMOS transistor to maintain saturation operation. This feedback system enables the circuit to operate reliably at low power supply voltages by dynamically compensating for voltage variations that would otherwise cause the transistor to exit saturation.
Solution Approach 2:
The patent dynamically adjusts the gate voltage parameter in response to temperature and operating condition changes, enabling the MOS transistor to maintain saturation operation even at low power supply voltages where the voltage margin is narrow. This parameter control expands the viable operating range at low voltages.
Data Source
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AI summary
A reference voltage circuit (100) includes a differential amplifier circuit (10) capable of stably operating at a constant voltage even if a collector voltage of an NPN transistor changes with temperature and is received. A voltage adjustment circuit (30) is included between commonly connected sources and commonly connected back gates of a first PMOS transistor (1) and a second PMOS transistor (2) serving as input parts of a differential amplifier circuit (10). A voltage generated by the voltage adjustment circuit (30) is adjusted to increase a source-back gate voltage of the first PMOS transistor (1) and the second PMOS transistor (2) in accordance with a voltage change in which the collector voltage of the NPN transistor received at one of the input parts of the differential amplifier circuit (10) decreases with a temperature rise.