Reference Voltage Training in Multi-Chip Memory Packages
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Solution Overview
Problem
As the degree of integration in memory devices increases, there is a need for effective methods to prevent operation errors among multiple memory devices within a single package, particularly in generating and managing reference voltages for DDR SDRAM memory devices.
Innovation Solution
A system that performs a reference voltage training operation by using a controller to output specific signal combinations with a semiconductor device, allowing it to enter training, ID setting, and ID selection modes to generate and manage voltage codes for reference voltages across multiple memory devices, ensuring accurate logic levels and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory devices are included in one package to increase integration, then productivity is improved, but operation errors increase among the memory devices
Solution Approach 1:
The patent implements feedback mechanisms through training operations where the semiconductor device adjusts reference voltage levels based on detected signal characteristics. The system continuously monitors data read/write operations and modifies voltage codes to optimize performance, thereby preventing operation errors in high-integration packages.
Solution Approach 2:
The patent changes electrical parameters by dynamically adjusting reference voltage levels through training operations. The system modifies voltage codes and voltage levels based on detected conditions, enabling precise control over memory device operations to prevent errors in multi-device packages.
2Manufacturing precision
If reference voltage training operation is performed to control voltage level, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the training operation mechanism universal by implementing it within the standard read/write operation flow of memory devices. The same hardware infrastructure used for normal data operations is leveraged to perform voltage level training, eliminating the need for separate dedicated training hardware and reducing overall device complexity.
Solution Approach 2:
The patent performs preliminary voltage level adjustment during manufacturing or initialization phases, where training operations are conducted to establish optimal reference voltage levels before the memory devices are deployed for normal operation. This preliminary action ensures precision is achieved without adding complexity to the main operational flow.
3Measurement precision
If training mode is used to generate voltage codes, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs voltage level training and voltage code generation during manufacturing or initialization phases as a preliminary action. Once the optimal voltage levels are established and stored, the memory devices can operate without repeated training operations, thereby achieving high measurement precision while minimizing time loss during actual data operations.
Solution Approach 2:
The patent implements self-service by enabling the memory device to automatically perform training operations and adjust its own reference voltage levels without external intervention. The device uses its internal infrastructure to detect signal characteristics and autonomously modify voltage codes, reducing the time and resources required for precision voltage level establishment.
Data Source
AI summary
A system to perform a reference voltage training operation may include: a controller configured to output a dock signal, a chip selection signal, a command address and data; and a semiconductor device configured to enter a training mode to control the level of a reference voltage when the chip selection signal and the command address are a first logic level combination in synchronization with the clock signal, configured to enter an ID setting mode to set a storage ID when the chip selection signal and the command address are a second logic level combination, and configured to enter an ID selection mode to update a voltage code that is generated in the training mode when the chip selection signal and the command address are a third logic level combination.