Referenceless CDR Training Using Data and Edge Pattern Detection
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Solution Overview
Problem
Conventional referenceless clock and data recovery (CDR) devices occupy large hardware area and consume high power due to their complex architecture.
Innovation Solution
A CDR device employing a data sampler, edge sampler, error detection circuit, and oscillation control circuit, which uses machine learning techniques to generate and adjust clock signals based on error signals derived from data and edge signals, optimizing hardware usage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional referenceless CDR device architecture is used, then clock and data signals can be recovered without external clock, but hardware area and power consumption increase
Solution Approach 1:
The CDR device is segmented into distinct functional blocks: data sampler, edge sampler, pattern detection circuit, and oscillation control circuit. Each block performs a specific function, allowing for optimized resource allocation and reduced overall hardware complexity while maintaining the referenceless operation capability
Solution Approach 2:
The oscillation control circuit serves multiple functions: it controls the oscillator to generate clock signals, adjusts clock frequency based on detected patterns, and maintains synchronization without external clock reference. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing hardware area
2Adaptability or versatility
If a conventional referenceless CDR device architecture is used, then clock and data signals can be recovered without external clock, but power consumption increases
Solution Approach 1:
By segmenting the device into data sampler, edge sampler, pattern detection circuit, and oscillation control circuit, power consumption is distributed and optimized across functional blocks. Each block can be designed with minimal power requirements for its specific function, reducing total power consumption while maintaining referenceless operation
Solution Approach 2:
The pattern detection circuit automatically detects patterns from sampled signals and generates control signals for the oscillation control circuit, which in turn adjusts the clock frequency. This self-regulating mechanism eliminates the need for external control circuits, reducing power consumption while maintaining the capability to recover signals without external clock
3Area of stationary object
If machine learning techniques are used to generate clock signals, then hardware area and power consumption are reduced, but system complexity in training increases
Solution Approach 1:
The machine learning model is trained in advance using historical data to learn the relationship between input signals and optimal clock generation. This preliminary training phase separates the complexity from the runtime operation, allowing the deployed device to have reduced hardware area while the training complexity is handled during the setup phase
Solution Approach 2:
The trained machine learning model parameters and weights are copied into the hardware implementation. The complex training process is performed once offline, and the resulting model is deployed in the hardware, separating training complexity from operational hardware requirements and reducing the hardware area needed for inference
Data Source
AI summary
A clock and data recovery (CDR) device includes a data sampler configured to output a data signal by sampling an input signal according to a first clock signal; an edge sampler configured to output an edge signal by sampling the input signal according to a second clock signal, the second clock signal having substantially the same frequency as the first clock signal and having substantially an opposite phase to the first clock signal; an error detection circuit configured to identify a plurality of patterns based on the data signal and the edged signal and generate an error signal according to occurrence frequencies of the identified plurality of patterns; and an oscillation control circuit configured to generate a first oscillation control signal to control an oscillator generating the first and second clock signal according to the error signal.