Referenceless Clock Recovery With Monotonic Frequency Acquisition
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Solution Overview
Problem
Conventional clock and data recovery systems with reference architectures face limitations in modern high-speed transmission interfaces due to the need for additional signal channels or crystal oscillators, and existing referenceless systems suffer from limited frequency acquisition ranges and sensitivity to data patterns and inter-symbol interference.
Innovation Solution
A referenceless clock and data recovery system with a frequency detector that includes an extraction circuit and a determination circuit to monotonically increase the clock signal frequency based on data and clock transition edges, eliminating the need for a reference signal and improving frequency acquisition range and robustness against inter-symbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a with-reference architecture is used for clock and data recovery, then frequency acquisition range is improved, but additional signal channels or crystal oscillators are required increasing device complexity
Solution Approach 1:
The patent extracts and eliminates the reference signal channel from the clock and data recovery system. By using a referenceless architecture with a frequency detector that compares data transition edges with clock edges, the system achieves frequency acquisition without requiring additional signal channels or crystal oscillators, thus reducing device complexity while maintaining adaptability
Solution Approach 2:
The frequency detector in the patent performs multiple functions: it detects frequency errors, determines whether to generate frequency-up conversion signals, and controls the voltage-controlled oscillator. This multi-functional approach eliminates the need for separate reference signal processing circuits, reducing overall device complexity while maintaining broad frequency acquisition capability
2Device complexity
If a referenceless architecture is used for clock and data recovery, then device complexity is reduced, but frequency acquisition range is limited and sensitivity to data patterns increases
Solution Approach 1:
The patent implements a dynamic frequency detection mechanism where the frequency detector continuously monitors the relationship between data transition edges and clock edges. Based on real-time comparison results, the system dynamically generates frequency-up conversion signals to adjust the clock frequency, enabling broad frequency acquisition range while maintaining simple referenceless architecture
Solution Approach 2:
The system changes the operating parameters of the voltage-controlled oscillator based on frequency detection results. By adjusting the oscillator frequency in response to detected frequency errors and generating frequency-up conversion signals when needed, the system achieves wide frequency acquisition range without increasing device complexity or sensitivity to data patterns
3Adaptability or versatility
If loop filter is reset during switching between frequency tracking loop and phase tracking loop, then adaptability is improved, but voltage surges occur affecting frequency acquisition
Solution Approach 1:
The patent maintains continuous frequency detection and adjustment without interrupting the frequency acquisition process. The frequency detector continuously compares data and clock edges and generates frequency-up conversion signals without interruption, eliminating voltage surges that would occur with loop filter resetting while maintaining adaptability through continuous frequency control
Data Source
AI summary
A system of referenceless clock and data recovery and a frequency detector thereof has been provided. The output clock of the system initially works at the lowest frequency, the frequency of the output clock is monotonically increased in accordance with the control of the frequency detector, thereby gradually approximating a target value. The edge extraction circuit receives the data signal and the clock signal, identifies the transition edges of the signals and generates a data transition signal and a clock transition signal representing the transition edges of the data signal and the transition edges of the clock signal respectively. The edge detector then determines the data period of the data signal and the clock period of the clock signal. When the data period is smaller than half of the clock period, the edge detector generates a frequency-up signal and the frequency of the output clock is increased.