Referenceless Clock Recovery Using Digital Frequency-Phase Detection
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Solution Overview
Problem
Conventional clock and data recovery circuits require reference oscillators, leading to increased cost, complexity, and power consumption, and struggle with high-frequency operations due to separate loop filters and analog components, which are area and temperature sensitive.
Innovation Solution
The implementation of referenceless clock and data recovery circuits using counter-based frequency and phase error detectors to generate recovered clock signals without a reference oscillator, eliminating the need for crystal oscillators and separate loop filters, and employing digital logic to stabilize the frequency and phase loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If reference oscillators (crystal oscillators) are used in conventional clock and data recovery circuits, then frequency stability is improved, but device complexity, power consumption, and cost increase
Solution Approach 1:
The patent extracts and eliminates the reference oscillator (crystal oscillator) from the conventional CDR circuit architecture. By removing this external reference component, the circuit achieves frequency locking through digital processing of the incoming data signal itself, thereby reducing device complexity and power consumption while maintaining frequency stability through the digital frequency detector and feedback mechanism
Solution Approach 2:
The patent replaces the mechanical/quartz-based reference oscillator with a digital logic-based frequency detection and generation system. The voltage-controlled oscillator is controlled by digital error signals from the frequency detector, substituting analog crystal resonance with digital frequency synthesis and control, which reduces complexity and power consumption
2Measurement precision
If separate loop filters and analog components are used in conventional CDR circuits, then frequency and phase control is improved, but semiconductor die area and temperature sensitivity increase
Solution Approach 1:
The patent merges the separate loop filters and analog components into a unified digital processing architecture. The digital frequency detector and phase detector integrate the functions previously performed by separate analog loop filters, eliminating the need for additional analog circuitry and reducing semiconductor die area while maintaining control precision through digital signal processing
Solution Approach 2:
The patent substitutes analog loop filters with digital filtering and processing mechanisms. The frequency and phase error detection is performed using digital logic circuits that process the incoming data signal transitions, replacing temperature-sensitive analog components with robust digital circuits that are less sensitive to temperature variations and occupy less die area
3Reliability
If reference oscillators and analog components are used in conventional CDR circuits, then clock and data recovery function is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the high-power reference oscillator from the circuit. By using the incoming data signal itself as the reference for frequency and phase detection, the circuit eliminates the continuous power consumption associated with maintaining a separate crystal oscillator, thereby reducing overall power consumption while maintaining recovery reliability
Solution Approach 2:
The patent implements a self-service mechanism where the incoming data signal provides its own frequency and phase reference information. The digital frequency detector extracts timing information directly from the data transitions, allowing the system to self-regulate without external power-intensive reference components, thus reducing power consumption while maintaining reliable operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, semiconductor die area, and cost while enabling stable high-frequency operations, improving bit error rates and reducing implementation challenges associated with analog components.
Implementation Method 1
first circuitry including a voltage-controlled oscillator, the first circuitry configured to generate a recovered clock signal
Implementation Method 2
the charge pump being configured to charge or discharge the capacitor when the difference represented by the one or more outputs of the second circuitry is outside the tolerance
Data Source
AI summary
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.