Referenceless Frequency Acquisition Using Digital Signal Processing
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Solution Overview
Problem
Conventional digital communication systems relying on external reference clocks and frequency detection circuits for clock and data recovery (CDR) in NRZ and PAM4 receivers are power-hungry and ineffective, especially for PAM4 modulation, where level transitions do not always cross the midpoint, limiting their ability to accurately lock onto unknown data frequencies within a narrow frequency range.
Innovation Solution
A purely digital referenceless frequency acquisition method using a digitally controlled oscillator (DCO) and digital signal processing techniques, such as deserializing data signals, generating parallel symbol streams, summing absolute values, and adjusting clock frequencies through feedback loops to lock onto the data frequency without additional clock phases or power-consuming components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external reference clock and frequency detection circuit are used for CDR, then frequency acquisition capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and eliminates the external reference clock circuit and frequency detection circuit from the CDR system. By removing these power-hungry components, the system achieves frequency acquisition capability through digital signal processing alone, significantly reducing power consumption while maintaining the ability to lock onto data frequency
Solution Approach 2:
The patent replaces the mechanical/electrical frequency detection circuit with a digital signal processing approach. The frequency acquisition function is implemented through digital correlation and feedback mechanisms rather than analog frequency detection, eliminating the need for power-consuming frequency detection hardware
2Measurement precision
If external reference clock is used for CDR, then frequency locking accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the external reference clock and its associated crystal oscillator components from the system. Frequency locking accuracy is achieved through digital correlation techniques and feedback control rather than external reference, simplifying the overall device architecture and reducing manufacturing complexity
Solution Approach 2:
The patent makes the CDR circuit self-sufficient by enabling it to acquire and lock onto frequency without external assistance. The digital signal processing unit performs multiple functions including frequency detection, phase alignment, and feedback control, eliminating the need for separate reference clock infrastructure
3Adaptability or versatility
If frequency detection circuit is used for CDR, then frequency acquisition range is improved, but power consumption doubles
Solution Approach 1:
The patent replaces the analog frequency detection circuit with a digital correlation-based frequency acquisition mechanism. This digital approach maintains the ability to detect and acquire a wide frequency range while consuming significantly less power, as digital processing can be performed efficiently without the power-hungry analog front-end required by traditional frequency detectors
4Use of energy by moving object
If conventional CDR loop is used with narrow frequency range, then power consumption is reduced, but frequency acquisition capability deteriorates
Solution Approach 1:
The patent implements a dynamic frequency acquisition mechanism that can adapt to wide frequency ranges. The digital correlation technique allows the system to dynamically search and lock onto the data frequency regardless of initial frequency offset, while the low-power digital implementation maintains energy efficiency throughout the frequency acquisition process
Data Source
AI summary
A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency. In subsequent iterations, proportional feedback to the DCO of lower rate sums of symbol streams is combined with integral feedback of codes representing finer approximations of the unknown data frequency swept over successively narrowing bands, and the DCO is locked to the finest approximation that lies between consecutive codes corresponding to sums having opposite signs.