Self-Aligned Interconnect Patterning via Reflected Lithography
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) shrink in size, proper alignment and overlay of material layers during lithography become increasingly difficult, leading to overlay errors that can cause electrical issues like reduced contact areas and short circuitry, and increase manufacturing costs due to the complexity and cost of lithography processes.
Innovation Solution
The use of a self-aligned lithography method where a resist layer is exposed to a combination of direct and reflected radiation, with the reflected exposure dose from conductive features ensuring that latent patterns are formed self-aligned with the conductive features, reducing overlay errors and enhancing exposure contrast.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used to pattern material layers, then manufacturing capability is maintained, but overlay errors increase as geometry sizes decrease, leading to reduced contact areas and electrical issues
Solution Approach 1:
The conductive features themselves serve as the alignment reference for pattern formation. The reflected radiation from conductive features creates latent patterns that are self-aligned with the conductive features, eliminating the need for separate alignment processes and reducing overlay errors that cause electrical performance degradation
Solution Approach 2:
The patent converts the harmful effect of reflected radiation (which causes exposure contrast issues) into a beneficial self-alignment mechanism. By controlling the exposure dose to be below the threshold for direct pattern formation but enabling pattern formation through reflected radiation, the previously harmful reflection becomes the primary mechanism for achieving precise self-alignment
2Manufacturing precision
If lithography processes are performed with tighter overlay margins to accommodate smaller geometry sizes, then manufacturing precision improves, but processing time and manufacturing costs increase
Solution Approach 1:
The self-aligned pattern formation process eliminates the need for multiple lithography steps and complex alignment procedures. By using a single exposure process where patterns form automatically aligned with conductive features through reflected radiation, processing time is reduced while maintaining high manufacturing precision
Solution Approach 2:
The conductive features are formed in advance before the lithography process, serving as pre-established alignment references. This preliminary formation of conductive features enables subsequent self-aligned patterning without requiring additional alignment steps, thereby reducing overall processing time
3Manufacturing precision
If conventional lithography with multiple exposure steps is used, then pattern accuracy can be maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the alignment reference function and the pattern formation function into a single process step. The same lithography exposure that forms patterns also uses reflected radiation from conductive features to ensure self-alignment, combining what would traditionally require separate alignment and patterning steps into one unified process
Solution Approach 2:
The lithography exposure process serves multiple functions simultaneously: it patterns the material layer, achieves self-alignment with conductive features, and ensures pattern accuracy all in one step. This multi-functionality eliminates the need for separate alignment procedures and reduces overall process complexity
4Productivity
If overlay margins are reduced to improve manufacturing efficiency, then productivity increases, but overlay errors increase leading to short circuitry and chip malfunction
Solution Approach 1:
The self-aligned pattern formation mechanism inherently maintains precise alignment without requiring large overlay margins. Patterns form automatically positioned relative to conductive features through reflected radiation, ensuring reliable electrical connections while enabling reduced overlay margins and improved manufacturing efficiency
Solution Approach 2:
The patent uses radiation (electromagnetic field) as the mechanism for self-alignment, analogous to using a field-based approach rather than mechanical alignment. The reflected radiation creates a field-based alignment reference that ensures precise positioning without requiring physical contact or complex mechanical alignment systems
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overlay errors, improves manufacturing efficiency, and decreases the overall cost of lithography by ensuring precise alignment and reducing the need for precise overlay margins, thereby enhancing the reliability and cost-effectiveness of semiconductor fabrication.
Implementation Method 1
A portion of the incident radiation reaches a top surface of the conductive features and is reflected as reflected radiation back to the photoresist layer
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.