Reflection Routing for Adaptive Modular Load Balancing in Multi-Hierarchy NoCs

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Solution Overview

Problem

As the number of cores on server chips increases, existing On-Die Interconnects (ODI) face challenges in supporting high throughput and efficiency, leading to bottlenecks and increased power consumption, particularly with the introduction of high bandwidth agents like High Bandwidth Memory (HBM) and new PCIe specifications, which demand more complex and power-hungry off-die interconnects.

Innovation Solution

A bounded hierarchical routing solution is introduced, utilizing a reflection network with node reflection and dimension order routing (DOR) to optimize throughput distribution across die-to-die connections and adapt to high bandwidth agents, featuring modular and scalable architecture with smaller Look-Up Tables (LUTs) and load balancing across hierarchical boundaries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing On-Die Interconnects (ODI) are used to support increasing number of cores, then the system can maintain current architecture, but throughput efficiency decreases and power consumption increases

Engineering Contradiction:
Improvethroughput efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies segmentation by dividing the interconnect network into multiple hierarchical levels (Level 0, Level 1, Level 2 networks) with different granularities. Each level handles specific routing patterns and credit flows, allowing the system to optimize for different traffic types independently rather than using a monolithic interconnect that handles all traffic uniformly, thereby improving throughput efficiency while reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the interconnect architecture, organizing networks in multiple levels where Level 0 is the finest granularity and Level 2 is the coarsest. This dimensional organization allows credit loops to be contained at appropriate levels and enables more efficient routing decisions, improving productivity while managing power consumption through localized rather than global credit management.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If high bandwidth agents like HBM and new PCIe specifications are introduced, then bandwidth capacity increases, but device complexity increases

Engineering Contradiction:
Improvebandwidth capacityVSAvoidinterconnect complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the interconnect into hierarchical levels where each level is designed to handle specific bandwidth requirements. Level 0 networks handle fine-grained traffic with lower complexity, while Level 2 networks handle coarse-grained high-bandwidth traffic. This segmentation allows the system to support high bandwidth agents like HBM without proportionally increasing overall system complexity, as each segment can be optimized independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate Level 1 networks that act as mediators between Level 0 and Level 2 networks. These intermediate networks provide buffer and routing capabilities that simplify the interface between high-bandwidth agents and the rest of the system, allowing bandwidth capacity to scale without linearly increasing complexity at any single level.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If complex off-die interconnects are used to support high bandwidth agents, then bandwidth capacity increases, but power consumption increases

Engineering Contradiction:
Improvebandwidth capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments credit management and routing functions across hierarchical levels, allowing credit loops to be contained at the appropriate level rather than requiring global credit management. This segmentation enables high bandwidth capacity at Level 2 while keeping power consumption manageable by localizing credit verification and routing decisions, avoiding the need for complex power-hungry off-die interconnects.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements self-service credit management where each hierarchical level maintains and verifies credits independently. Level 0 networks manage their own credits, Level 1 networks manage intermediate credits, and Level 2 networks manage top-level credits. This self-service approach eliminates the need for centralized credit management that would require complex high-power interconnects, while still supporting high bandwidth capacity through the hierarchical structure.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11949595B2Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips
Publication Date: 2024.04.02 INTEL CORP
  • US11949595B2 patent drawing
  • US11949595B2 patent drawing
  • US11949595B2 patent drawing

AI summary

An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.