Programmable Reflective Load Lines for Broadband Quasi-True Time Delay
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Solution Overview
Problem
Existing beamforming technologies face challenges in achieving compact size, precise phase resolution, and wide bandwidth while maintaining low insertion loss and power consumption, particularly in mobile applications.
Innovation Solution
The integration of programmable reflective load lines with sub-wavelength footprints and 3D variable reflectors in CMOS technology, utilizing hybrid couplers and programmable reflective load lines with tunable capacitance and switches, allows for precise phase tuning and time delay across a wide bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If typical phase shifters are used to occupy small footprint, then area is reduced, but frequency dependence is introduced limiting bandwidth
Solution Approach 1:
The patent transitions from planar 2D phase shifters to 3D volumetric structures by stacking multiple metal layers vertically. This dimensional change enables the signal to travel through multiple stacked delay segments, achieving true time delay functionality in a compact footprint while maintaining broadband performance across frequency variations.
Solution Approach 2:
The delay path is divided into multiple discrete delay segments arranged in series between signal paths. Each segment contributes a portion of the total delay, allowing the system to achieve precise time delay control while maintaining a compact structure. The segmented approach also enables independent optimization of each segment for broadband performance.
2Productivity
If true time delay elements are used to prevent beam squint and boost channel capacity, then channel capacity is improved, but chip area becomes prohibitively large
Solution Approach 1:
The patent uses vertically stacked metal layers to create 3D delay paths, enabling TTD functionality in a minimal footprint. By utilizing the vertical dimension through multiple stacked segments, the design achieves the required delay range for high channel capacity without occupying prohibitively large chip area.
Solution Approach 2:
Multiple delay segments are nested within each other by stacking them in vertical layers. The signal traverses through these nested segments in sequence, accumulating the total delay. This nesting approach compresses what would otherwise be a long horizontal delay path into a compact vertical structure, achieving high delay range in minimal area.
3Loss of time
If cascade of transmission lines is used to implement time delay, then time delay is achieved, but insertion loss and noise increase
Solution Approach 1:
The total delay is segmented into multiple shorter delay segments rather than using a single long transmission line. Each segment contributes a portion of the total delay, and by optimizing each segment individually, the overall insertion loss is reduced compared to a single long delay line. The segmented structure also improves bandwidth performance.
4Measurement precision
If transistor switches are used to tune time delay, then phase resolution is improved, but insertion loss and nonlinearity increase
Solution Approach 1:
The patent replaces active transistor switches with passive switching mechanisms implemented through the geometric configuration of 3D printed metallic structures. The switching action is achieved by selectively connecting different delay segments through passive elements, eliminating the insertion loss and nonlinearity associated with active transistor switches while maintaining precise phase control.
Data Source
AI summary
An integrated circuit includes a programmable reflective load line that includes main delay segments arranged in series between an input of the programmable reflective load line and ground, variable delay modules arranged in parallel between nodes adjoining the main delay segments and ground, and main switches, with each main switch arranged between one of the variable delay modules and one of the nodes adjoining the main delay segments. Each variable delay module includes sub-delay segments arranged in series between the associated main switch and ground. Each variable delay module also includes one or more sub-delay switches, with each sub-delay switch arranged between a node adjoining two of the associated sub-delay segments and ground. The integrated circuit may further include a hybrid coupler arranged with the programmable reflective load line and another programmable reflective load line as a reflective-type phase-shifter.