Refractory Metal Dumbbell Vias for Semiconductor Interconnects

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Solution Overview

Problem

Copper interconnect structures in semiconductor devices are prone to void formation due to diffusion at high temperatures and stress concentration at junctions, leading to electrical opens and reduced chip yield.

Innovation Solution

The use of refractory metals or alloys to form vias with 'dumbbell' or 'barbell' shaped structures that extend beyond the edges of the via openings, incorporating diffusion barrier layers and refractory metal fillings to reduce void formation by covering hot spots with slower diffusing metals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper is used to form interconnect structures, then electrical conductivity is improved, but void formation occurs due to diffusion at high temperatures

Engineering Contradiction:
Improveelectrical conductivityVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The via structure is segmented into multiple portions: a first portion extending below the via opening into the lower interconnect-level dielectric layer, and a second portion extending above the via opening into the upper interconnect-level dielectric layer. This segmentation distributes the stress and diffusion resistance across different regions, preventing void formation while maintaining electrical conductivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via structure transitions from a simple vertical conduit to a three-dimensional structure with lateral extensions. The first and second portions extend laterally beyond the edges of the via opening, creating a dumbbell or barbell shape. This dimensional change increases the surface area for stress distribution and diffusion barrier effectiveness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If copper interconnect structures are formed with standard via structures, then manufacturing is simplified, but stress concentration at junctions creates hot spots for void formation

Engineering Contradiction:
Improvevia structure fabricationVSAvoidstress concentration
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The via structure implements local quality by having different geometries at different locations. The first portion extends laterally beyond the lower edges of the via opening to reduce stress concentration at the lower junction. The second portion extends laterally beyond the upper edges to reduce stress concentration at the upper junction. This localized geometric modification addresses stress concentration problems at specific hot spots without complicating the overall manufacturing process.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces void formation and enhances the reliability of interconnect structures by utilizing refractory metals that withstand higher temperatures and improve adhesion, thereby improving chip yield and reducing electrical defects.

Implementation Method 1

copper tends to diffuse at typical semiconductor processing temperatures. As a result, copper interconnect structures may form voids during thermal cycling

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

via formed using a refractory metal or alloy of refractory metals... which can withstand higher temperatures than copper

Methodology Applied
Scientific EffectThermal stability:

Data Source

PatentUS11551967B2Via structure and methods for forming the same
Publication Date: 2023.01.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11551967B2 patent drawing
  • US11551967B2 patent drawing
  • US11551967B2 patent drawing

AI summary

Vias and methods of making the same. The vias including a middle portion located in a via opening in an interconnect-level dielectric layer, a top portion including a top head that extends above the via opening and extends laterally beyond upper edges of the via opening and a bottom portion including a bottom head that extends below the via opening and extends laterally beyond lower edges of the via opening. The via may be formed from a refractory material.