Refresh Address Generator for Volatile Memory

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Solution Overview

Problem

Conventional volatile memory devices face increased refresh overhead due to the growing number of memory cells with retention times shorter than the standard refresh period as memory cell sizes shrink, necessitating more redundancy rows.

Innovation Solution

A refresh address generator is introduced, comprising a refresh sequence buffer and a refresh address generating unit that groups memory cell rows by data retention characteristics, generating optimized refresh row addresses based on a sequence stored in the buffer, and dynamically adjusts refresh periods as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cell size is reduced to increase storage capacity, then storage density is improved, but the number of memory cells with short retention times increases, requiring more redundancy rows and increasing refresh overhead

Engineering Contradiction:
Improvestorage capacityVSAvoidrefresh overhead
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent segments memory cell rows into multiple groups based on their data retention characteristics. Each group is assigned a different refresh period, allowing the system to optimize refresh operations for each segment rather than applying a uniform refresh schedule to all rows. This segmentation enables reduced refresh overhead for groups with longer retention times while maintaining data integrity for all memory cells.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic refresh period adjustment based on measured data retention characteristics. The refresh period for each memory cell row group is not fixed but is determined and adjusted according to actual retention performance. This dynamic approach allows the system to adapt refresh schedules to varying retention characteristics, reducing unnecessary refresh operations and lowering overall refresh overhead.

Inventive Principle:
Principle #15Dynamics

2Reliability

If more redundancy rows are added to handle short retention times, then data reliability is improved, but device complexity and refresh overhead increase

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidredundancy row structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different refresh periods to different groups of memory cell rows based on their specific retention characteristics. Instead of treating all rows uniformly or adding extensive redundancy, the system tailors the refresh approach to each group's needs. This localized optimization maintains data reliability for each group while avoiding the complexity of uniform redundancy structures.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If conventional uniform refresh schedule is used for all memory cell rows, then implementation simplicity is maintained, but refresh efficiency decreases due to unnecessary refresh operations on rows with longer retention times

Engineering Contradiction:
Improverefresh schedule implementationVSAvoidrefresh efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent transitions from a static uniform refresh schedule to a dynamic differentiated refresh schedule. The refresh period for each memory cell row group is determined based on measured retention characteristics and can be adjusted accordingly. This dynamic approach significantly improves refresh efficiency by eliminating unnecessary refresh operations on rows with longer retention times while maintaining data integrity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9275717B2Refresh address generator, volatile memory device including the same and method of refreshing the volatile memory device
Publication Date: 2016.03.01 SAMSUNG ELECTRONICS CO LTD
  • US9275717B2 patent drawing
  • US9275717B2 patent drawing
  • US9275717B2 patent drawing

AI summary

A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.