Refresh Circuit for Row Hammer Mitigation in Memory Arrays
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Solution Overview
Problem
As semiconductor storage devices increase in density, memory cells experience reduced physical volume and noise tolerance, leading to increased electromagnetic interference and data loss due to the 'row hammer effect', where frequently accessed word lines cause excessive charge loss in adjacent cells, necessitating timely and effective refresh mechanisms.
Innovation Solution
A refresh circuit that selects between normal and redundant word line logical addresses, generates a seed address, and converts it into a physical address for the memory array to perform a refresh operation, ensuring timely refresh of adjacent word lines to prevent data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to improve storage capacity, then storage capacity is improved, but noise tolerance and electromagnetic interference resistance deteriorate
Solution Approach 1:
The memory array is segmented into normal word lines and redundant word lines. The refresh circuit selectively refreshes only the redundant word lines adjacent to frequently accessed normal word lines, rather than refreshing all word lines uniformly. This segmentation allows targeted mitigation of electromagnetic interference effects without sacrificing overall storage capacity.
Solution Approach 2:
The refresh operation is applied locally only to specific word lines that are adjacent to frequently accessed normal word lines, rather than uniformly to all word lines. The refresh circuit identifies victim word lines based on access patterns and applies refresh operations only to those specific locations where electromagnetic interference is most likely to cause data loss.
2Reliability
If refresh operations are performed on all word lines to prevent data loss, then data reliability is improved, but access speed and efficiency deteriorate
Solution Approach 1:
The refresh circuit performs preliminary identification of victim word lines by monitoring access patterns of normal word lines. Before data loss occurs, the circuit pre-identifies which redundant word lines are adjacent to frequently accessed normal word lines and schedules refresh operations for those specific lines, preventing data loss without requiring full-array refresh.
Solution Approach 2:
Instead of performing refresh operations on all word lines (excessive action), the circuit performs refresh operations only on the subset of redundant word lines that are adjacent to frequently accessed normal word lines (partial action). This partial refresh approach maintains data reliability for vulnerable cells while significantly reducing the overhead compared to full-array refresh.
3Reliability
If redundant word lines are added to compensate for data loss, then data reliability is improved, but device complexity increases
Solution Approach 1:
The redundant word lines serve multiple functions: they act as backup storage for data protection, and simultaneously serve as the target for selective refresh operations to mitigate electromagnetic interference. The refresh circuit itself performs multiple functions by monitoring access patterns, identifying victim word lines, and executing selective refresh operations. This multi-functionality reduces the need for additional dedicated components.
Solution Approach 2:
The refresh circuit uses the existing access pattern information from normal word line operations to automatically identify which redundant word lines need refreshing. The system self-services by utilizing its own operational data (access patterns) to determine refresh requirements, without requiring external control signals or additional sensing mechanisms for each word line.
Data Source
AI summary
A refresh circuit includes signal selector configured to select one of normal and redundant word line logical addresses as output, output signal of which is designated as first logical address; row address latch connected to output terminal of signal selector and configured to output row hammer address and row hammer flag signal according to first logical address; seed arithmetic unit connected to output terminal of row address latch and configured to generate seed address according to row hammer address; logical arithmetic unit connected to output terminal of seed arithmetic unit and configured to obtain row hammer refresh address according to seed address, row hammer refresh address is adjacent physical address of seed address; and pre-decode unit connected to output terminal of logical arithmetic unit and configured to receive row hammer refresh address, and convert it into physical address to be used by memory array of memory to perform refresh operation.