Refresh Circuit Multi-Enable Skew Operation Peak Current Reduction
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Solution Overview
Problem
Conventional DRAM refresh operations increase noise peak values and peak current due to the simultaneous activation of a large number of rows, making it difficult to minimize or reduce peak current as memory density increases.
Innovation Solution
A refresh circuit that performs a multi-enable skew refresh operation by generating refresh signals with different timings for distinct memory groups or banks, enabling refresh target lines in non-coinciding operation periods to distribute the refresh workload and reduce peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of rows are activated simultaneously during refresh operation, then the refresh operation can be completed within the required time period, but the noise peak value increases and peak current increases
Solution Approach 1:
The memory device is divided into multiple independent memory banks (first memory bank, second memory bank, etc.). Each memory bank can be refreshed independently with its own row activation schedule. This segmentation allows the refresh operation to distribute the activation load across multiple banks rather than activating all rows simultaneously in a single bank, thereby reducing peak current and noise while maintaining overall refresh productivity.
2Quantity of substance
If memory density increases, then the storage capacity improves, but it becomes more difficult to minimize or reduce peak current during refresh operations
Solution Approach 1:
As memory density increases, the segmentation into multiple memory banks becomes even more critical. Each memory bank contains a portion of the total memory capacity, and refreshing multiple banks in parallel or in a staggered sequence distributes the peak current demand across different time periods or simultaneous independent channels, preventing the peak current from scaling linearly with total memory capacity.
Solution Approach 2:
The refresh operation transitions from a single-dimension sequential row activation within one bank to a multi-dimensional approach where multiple banks are activated simultaneously or in staggered sequences. This adds the bank dimension to the refresh operation, allowing parallel processing of refresh tasks across different memory banks, thereby managing peak current despite increased memory density.
Data Source
AI summary
A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.