Refresh Circuit Staggered Memory Bank Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor apparatuses, particularly volatile ones, efficient refresh operations for multiple memory banks are challenging due to the need for optimized time management and differentiated refresh strategies to maintain data integrity.
Innovation Solution
A refresh circuit is designed to perform a first refresh operation for all memory banks within a predetermined time frame, followed by a second refresh operation for partially completed banks, utilizing a control block for generating pre-control signals and additional refresh flags, and a switching block to alter the order of memory bank refreshes based on bank count signals and row active signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first refresh operation is performed for all memory banks within a first time period, then data integrity is maintained across all banks, but the refresh time consumed is increased
Solution Approach 1:
The patent divides the refresh operation into two segments: a first refresh operation for all memory banks, and a second refresh operation for only those banks that completed the first refresh. This segmentation allows the system to maintain data integrity for all banks while reducing the total refresh time by avoiding redundant refreshes of banks already in a valid state.
Solution Approach 2:
The patent implements partial action by performing the second refresh operation only on a subset of memory banks (those that completed the first refresh) rather than all banks. This partial refresh approach reduces the overall refresh time while still maintaining data integrity for the entire memory system.
2Loss of time
If a second refresh operation is performed for partial memory banks that completed the first refresh, then the refresh time is reduced, but the complexity of controlling the refresh operations increases
Solution Approach 1:
The patent uses feedback mechanisms through additional refresh flags and bank count signals that track the completion status of memory banks. The control block monitors which banks have completed their first refresh operation and uses this feedback information to selectively activate the second refresh operation only for the appropriate banks, thereby managing complexity through systematic state tracking.
Solution Approach 2:
The patent introduces intermediary control elements including a control block, additional refresh flags, and bank count signals that mediate between the refresh commands and the memory banks. These intermediaries manage the complexity by providing a structured interface for tracking and controlling the refresh state of each bank, simplifying the overall control logic.
3Productivity
If refresh operations are staggered across multiple time periods, then the refresh efficiency is improved, but the control signal generation becomes more complex
Solution Approach 1:
The patent implements periodic action through staggered refresh operations occurring in distinct time periods. The first refresh operation occurs in an initial time period, and the second refresh operation occurs in a subsequent time period for banks that completed the first refresh. This periodic structure improves refresh efficiency by allowing overlapping operations while maintaining systematic control through time-based segmentation.
Data Source
AI summary
A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period.