Refresh Circuit Counting Logic for Internal Memory Timing Adjustment

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Solution Overview

Problem

Semiconductor memory devices face challenges in adjusting their refresh cycles internally, requiring external timing adjustments for refresh commands, which limits operational flexibility and efficiency.

Innovation Solution

A refresh circuit that generates counting signals to decode multiple preliminary refresh cycle change signals, allowing internal adjustment of refresh cycles based on external settings or error signals, enabling simultaneous enablement of multiple word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the refresh cycle is changed by adjusting external timing of refresh commands, then the refresh cycle can be modified, but the operational flexibility and efficiency are limited due to inability to change refresh cycle internally

Engineering Contradiction:

Improverefresh cycle adjustabilityVSAvoidoperational flexibility

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The refresh circuit autonomously counts refresh commands and generates refresh cycle change signals internally without requiring external control logic. The circuit monitors its own operation and automatically adjusts the refresh cycle based on counted refresh commands, enabling the system to self-regulate its refresh timing.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

A refresh cycle control circuit is introduced as an intermediary component that receives refresh commands, counts them, decodes the count value, and generates appropriate refresh cycle change signals. This intermediary layer translates external refresh commands into internal control signals that adjust the refresh cycle, bridging the gap between external timing requirements and internal refresh control.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the refresh circuit counts and decodes refresh commands to generate multiple preliminary refresh cycle change signals, then internal refresh cycle adjustment is enabled, but the device complexity increases

Engineering Contradiction:

Improveinternal refresh cycle controlVSAvoidcircuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The refresh cycle control circuit performs multiple functions within a single integrated structure: it counts refresh commands, decodes the count values, generates multiple preliminary refresh cycle change signals, and selects the appropriate signal based on decoded results. This multi-functional design consolidates what could be separate circuits into one unified component, managing complexity while enabling internal refresh cycle adjustment.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The refresh control functionality is divided into distinct operational stages: counting stage (monitoring refresh commands), decoding stage (converting count values to control signals), and execution stage (generating refresh cycle change signals). This segmentation allows each sub-function to be optimized independently while working together as a coordinated system, making the overall complex function more manageable and implementable.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12387777B2Refresh circuit and semiconductor memory device including the same

Publication Date: 2025.08.12 SK HYNIX INC

AI summary

A refresh circuit is configured to generate a counting signal by counting a refresh command and to generate a plurality of preliminary refresh cycle change signals by decoding the counting signal. The refresh circuit is also configured to change a refresh cycle based on one of the plurality of preliminary refresh cycle change signals and to perform a refresh operation.