Refresh Control Circuit for Semiconductor Memory Adaptive Address Sequencing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in varying the sequence of refresh addresses, leading to data loss in cells with insufficient retention time due to a fixed refresh period based on average retention time, which cannot adapt to individual cell needs.
Innovation Solution
A refresh control circuit and method that allows for varying the sequence of refresh addresses based on external addresses in a test mode, using a refresh counter, external address input buffer, address selector, and row address decoder to generate a row address selection signal for the cell array, enabling adaptive refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed refresh period based on average retention time is used, then the refresh operation can be simplified and standardized, but cells with insufficient retention time will lose data due to inability to adapt to individual cell needs
Solution Approach 1:
The patent implements dynamic refresh address sequencing by allowing the refresh counter to be overridden by external address inputs during test modes. The address selector circuit dynamically switches between using the refresh counter sequence or external addresses based on mode selection signals, enabling adaptive refresh timing for individual cells with different retention characteristics while maintaining a relatively simple overall circuit structure.
Solution Approach 2:
The patent changes the refresh address parameter from a fixed counter-based sequence to variable external addresses during test modes. This allows the refresh operation to adapt to different retention times by accepting external address inputs that can be adjusted according to individual cell needs, while the normal mode maintains the simple fixed sequence for standard operation.
2Reliability
If the refresh operation is performed at a period determined based on average retention time, then the refresh control can be simplified, but cells with insufficient retention time cannot retain data properly
Solution Approach 1:
The system provides dynamic control where the refresh address can be selected from either the counter sequence or external addresses based on mode signals. During normal operation, the simple counter sequence is used for ease of operation. During test modes, external addresses can be provided to adapt to individual cell retention characteristics, improving reliability without complicating normal operation.
Solution Approach 2:
The address selector circuit acts as an intermediary between the simple refresh counter and the external address inputs. It mediates between the need for simple controlled operation in normal mode and the need for adaptive control in test modes, allowing external addresses to be introduced only when needed for reliability testing without affecting normal ease of operation.
3Adaptability or versatility
If the sequence of refresh addresses is fixed, then the refresh control circuit can be simplified, but the amount of generated noise cannot be varied for cell screening
Solution Approach 1:
The address selector circuit dynamically switches between using the refresh counter sequence for normal operation and accepting external addresses for test modes. This dynamic capability allows the system to vary noise levels and address sequences for cell screening when needed, while maintaining a relatively simple circuit structure that only adds complexity during test operations, not during normal use.
Data Source
AI summary
A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address.