Refresh Control Circuit for DRAM Current Loss Reduction
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Solution Overview
Problem
In self-refresh mode of Dynamic Random Access Memory (DRAM), repeated switching between refresh and idle states leads to current loss, adversely affecting memory performance.
Innovation Solution
A refresh control circuit comprising a processing circuit, logic circuit, and power supply circuit that processes refresh command signals to generate a target control signal, allowing centralized power supply for multiple refresh operations, reducing switching times of the power supply circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory repeatedly switches between refresh state and idle state for multiple refresh operations, then the refresh operations can be completed, but current loss increases and memory performance deteriorates
Solution Approach 1:
The patent merges multiple refresh operations into a single continuous refresh state by combining multiple refresh command signals into one refresh period. The power supply circuit remains activated throughout the entire duration of multiple refresh operations, avoiding repeated switching between on and off states. This consolidation reduces the number of power supply switching events, thereby minimizing current loss while ensuring all refresh operations are completed.
2Ease of operation
If the power supply circuit switches on and off for each refresh operation, then individual refresh operations can be controlled, but the switching frequency increases and current loss worsens
Solution Approach 1:
The processing circuit combines multiple refresh command signals that occur within a specified time window into a single extended refresh period. The power supply circuit receives this combined signal and maintains a continuous on-state throughout the entire duration, eliminating the need for multiple individual switching events. This approach simplifies the power supply control mechanism while maintaining precise control over the refresh operations.
3Productivity
If multiple refresh operations are performed with separate power supply switching, then each operation can be independently controlled, but the total switching time increases and overall performance decreases
Solution Approach 1:
The patent ensures continuous power supply activation throughout the entire sequence of multiple refresh operations. By maintaining the power supply circuit in a continuous on-state without interruption or repeated switching, the useful action of refreshing memory continues uninterrupted. This eliminates the time lost to repeated power supply switching events, thereby improving overall refresh operation throughput and memory performance.
Data Source
AI summary
A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.