Refresh Control Circuit for DRAM Weak Cell Detection
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Solution Overview
Problem
As semiconductor devices become more integrated, the reduced distance between memory cells and word lines leads to data interference, necessitating a refresh operation to prevent data loss in DRAM devices due to varying electric charges in cell capacitors.
Innovation Solution
A semiconductor device incorporating a refresh control circuit that generates test addresses based on a refresh signal and detection clock signal, senses logic levels of internal data, and uses an address storage circuit to divide and store these addresses for performing additional refresh operations on weak cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between memory cells and word lines is reduced to increase integration, then device integration density is improved, but data interference between adjacent cells increases causing data loss
Solution Approach 1:
The patent applies preliminary action by performing a refresh operation on memory cells before data is actually lost. The system detects weak cells that are prone to data loss due to interference, and proactively refreshes them during idle periods or when not actively accessed, preventing data loss before it occurs.
Solution Approach 2:
The patent implements feedback by monitoring the status of memory cells to identify weak cells that are susceptible to data loss from interference. This feedback mechanism allows the system to adaptively determine which cells need refresh operations, enabling targeted intervention based on actual cell conditions rather than uniform refreshing of all cells.
2Reliability
If a refresh operation is performed on all memory cells to prevent data loss, then data retention is improved, but operation time and power consumption increase
Solution Approach 1:
The patent applies local quality by differentiating between weak cells and normal cells, and applying refresh operations only to weak cells. Instead of uniformly refreshing all memory cells, the system identifies cells with data loss susceptibility and targets refresh operations specifically to those locations, making the refresh process localized and efficient.
Solution Approach 2:
The patent implements partial action by performing refresh operations on only a subset of memory cells (weak cells) rather than all cells. This partial refreshing approach is sufficient to maintain data integrity for vulnerable cells while avoiding the time and power overhead of refreshing all cells in the memory array.
3Reliability
If additional refresh operations are performed on weak cells to address interference, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling memory cells to effectively refresh themselves during write operations to adjacent banks. When a write operation occurs in an adjacent bank, the refresh operation to the current bank can be postponed or integrated, allowing the memory system to utilize existing operational windows for refresh without requiring dedicated separate refresh control logic.
Data Source
AI summary
A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.