Refresh Control Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory devices perform refresh operations based on average retention time, leading to data loss in cells with insufficient retention time, as they apply a uniform refresh period regardless of cell characteristics, and may not adequately address PVT variations and peak current requirements.
Innovation Solution
A refresh control circuit and method that enables a refresh operation twice during one refresh row cycle time, with internal refresh rates adjusted to 4K/32 ms to reinforce cells with short retention capacity, while maintaining external refresh rates at 8K/64 ms, and includes a refresh controller to manage refresh signal enablement and row address decoding for sequential access within the cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform refresh period is applied to all cells based on average retention time, then the refresh operation is simplified and can be performed at a standard rate, but cells with insufficient retention time experience data loss
Solution Approach 1:
The refresh operation is segmented into two distinct modes: auto refresh mode for cells with adequate retention time and self refresh mode for cells with insufficient retention time. The refresh controller divides the cell array into different refresh groups and applies different refresh strategies to each group, ensuring that all cells receive appropriate refresh treatment based on their specific retention characteristics
Solution Approach 2:
The refresh control system dynamically adjusts the refresh period and mode based on cell characteristics and operating conditions. The refresh controller can switch between auto refresh and self refresh modes, and adjust refresh timing internally to match the specific retention requirements of different cell groups, making the refresh operation adaptive rather than static
2Reliability
If the refresh rate is increased to reinforce cells with short retention capacity, then data retention reliability improves, but peak current requirements increase
Solution Approach 1:
Different refresh rates and modes are applied to different regions or groups of cells based on their specific retention requirements. Cells with short retention capacity are targeted with enhanced refresh operations (self refresh mode with shorter periods) while cells with adequate retention use standard auto refresh, optimizing power consumption by applying enhanced refresh only where necessary
Solution Approach 2:
The refresh controller implements periodic refresh operations with varying periods based on cell group requirements. By using shorter refresh periods selectively for vulnerable cells rather than uniformly across all cells, the system maintains data retention reliability while limiting peak current draw to only when and where needed
3Productivity
If internal refresh rate is increased to 4K/32 ms to reinforce cells with short retention capacity, then productivity increases, but the refresh cycle time must be extended
Solution Approach 1:
The refresh controller merges multiple refresh operations into a coordinated sequence that achieves higher effective refresh rates for critical cells. By combining auto refresh and self refresh operations and overlapping their execution, the system achieves the equivalent of 4K/32 ms refresh throughput without requiring a single extended refresh cycle, as different cell groups are refreshed in parallel or overlapping time windows
Data Source
AI summary
A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.