Refresh Control Circuit for Semiconductor Memory Devices
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Solution Overview
Problem
Semiconductor memory devices face inefficiencies in refresh operations due to the need to periodically refresh all memory cells, including redundant ones not involved in repair, which increases operational load and can lead to data loss.
Innovation Solution
A refresh control circuit and method that selectively performs refresh operations only on redundant word lines used for repairing defective cells, utilizing a redundant reset signal and address generation to optimize the refresh process by omitting unnecessary operations on unused redundant word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh operation is performed on all memory cells including redundant ones, then data loss is prevented, but operational load increases significantly
Solution Approach 1:
The patent extracts and identifies only the necessary redundant word lines that require refresh operations by detecting repair addresses from fuse circuits. The refresh operation is then applied selectively to these identified word lines rather than all redundant word lines, thereby reducing operational load while maintaining data retention reliability.
2Reliability
If a refresh operation is performed on all redundant word lines, then data loss is prevented, but refresh time increases
Solution Approach 1:
The patent extracts the specific subset of redundant word lines that require refresh by detecting repair addresses stored in fuse circuits. By identifying only these necessary word lines and excluding unused redundant word lines from the refresh operation, the patent reduces the total refresh time while ensuring data retention reliability for the active memory cells.
3Productivity
If refresh operations are performed on unused redundant word lines, then operational load is reduced, but device complexity increases
Solution Approach 1:
The patent implements a self-service mechanism where the fuse circuits automatically store repair address information that identifies which redundant word lines are in use. The refresh control circuit utilizes this pre-stored information to automatically determine the necessary refresh scope without requiring external control or complex decision-making logic, thereby achieving refresh efficiency improvement with minimal increase in device complexity.
Data Source
AI summary
A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.