Refresh Control Circuit for Row Hammer Mitigation
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Solution Overview
Problem
In densely packed semiconductor storage devices, the electromagnetic interaction between memory cells increases, leading to reduced noise tolerance and higher possibilities of data loss due to the 'row hammer effect', where frequent activation of word lines causes excessive charge loss in adjacent cells before refresh signals can replenish them.
Innovation Solution
A refresh control circuit is introduced, comprising a random output sub-circuit that receives and outputs single-row addresses, a row hammer address generation sub-circuit, and a signal selector to manage refresh commands, ensuring timely and efficient refresh of row hammer addresses by prioritizing high-frequency and timeout addresses, thereby reducing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage capacity is improved, but electromagnetic interaction between cells increases causing data loss
Solution Approach 1:
The refresh control circuit proactively identifies and refreshes row hammer addresses before data loss occurs. By monitoring word line activation patterns and pre-refreshing adjacent addresses that are likely to be affected, the system prevents electromagnetic interaction from causing data loss, thus maintaining high storage capacity without suffering from the harmful effects of cell density increases
2Speed
If word lines are activated frequently, then memory access speed is improved, but charge loss in adjacent cells increases
Solution Approach 1:
The refresh control circuit continuously monitors word line activation patterns and uses this feedback to identify addresses susceptible to row hammer effects. By tracking which word lines are frequently activated and which adjacent addresses are at risk, the system dynamically adjusts refresh operations to prevent charge loss while maintaining high memory access speeds through selective rather than blanket refresh approaches
3Reliability
If refresh operations are performed on all addresses, then data integrity is maintained, but system efficiency decreases
Solution Approach 1:
Instead of uniformly refreshing all memory addresses, the refresh control circuit applies refresh operations selectively to specific addresses identified as being at risk from row hammer effects. By analyzing word line activation patterns and targeting only the adjacent addresses that show signs of charge loss, the system maintains data integrity in vulnerable regions while avoiding unnecessary refresh operations elsewhere, thus preserving system efficiency
Data Source
AI summary
A refresh control circuit includes: a random output sub-circuit for sequentially receiving n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses being greater than a preset duration, the m single-row addresses ranking top m in occurrence frequency, the L single-row addresses corresponding to word lines turned on between adjacent refresh commands, n being a natural number, and m being a positive integer; and for receiving a first random number which is a positive integer less than or equal to n+m, and then outputting an i-th received single-row address, i being equal to the first random number; and a row hammer address generation sub-circuit for outputting a row hammer address corresponding to the received single-row address acting as a refresh object corresponding to the refresh command.