Refresh Control Circuit for DRAM Rowhammer Mitigation
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Solution Overview
Problem
Volatile memory devices, such as DRAM, face issues with rowhammer effects due to intense access of certain rows affecting adjacent rows, leading to data corruption and inefficient refresh operations as memory cell density increases.
Innovation Solution
A memory device with a refresh control circuit that includes registers to store row addresses and counters to track access hits, allowing for stochastic replacement of row addresses and identification of victim rows for refresh, thereby managing rowhammer effects and optimizing refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage capacity is improved, but rowhammer effects worsen due to increased influence of adjacent row voltages
Solution Approach 1:
The refresh control circuit proactively identifies intensively accessed rows and refreshes adjacent victim rows before data corruption occurs. By performing preliminary refresh operations on potentially affected rows, the system prevents rowhammer-induced data loss rather than reacting after damage occurs.
Solution Approach 2:
The system uses hit counters to monitor access frequencies of different rows and provides feedback to the refresh control logic. This feedback mechanism enables dynamic identification of intensively accessed rows and adjusts refresh operations accordingly, allowing the system to adapt to changing access patterns and mitigate rowhammer effects in real-time.
2Reliability
If conventional refresh operations are used, then memory stability is maintained, but refresh efficiency deteriorates due to inability to identify victim rows
Solution Approach 1:
Instead of uniformly refreshing all rows, the system applies refresh operations selectively to specific victim rows adjacent to intensively accessed rows. This localized approach concentrates refresh resources where they are most needed, improving overall refresh efficiency while maintaining memory stability.
Solution Approach 2:
The system changes the refresh strategy from time-based uniform refresh to access-pattern-based selective refresh. By monitoring hit counters and identifying rows with high access frequencies, the system dynamically adjusts which rows require refresh, optimizing refresh operations based on actual usage patterns rather than fixed schedules.
3Device complexity
If row addresses are deterministically managed, then control simplicity is maintained, but detection accuracy worsens due to inability to track access patterns
Solution Approach 1:
The hit counters serve as intermediary components that bridge simple address management and complex access pattern detection. These counters accumulate access frequency information without complicating the basic row address management logic, enabling accurate detection of intensively accessed rows while maintaining relatively simple control structures.
Solution Approach 2:
The system pre-allocates hit counters for each row address and continuously accumulates access frequency data in the background. This preliminary tracking of access patterns enables accurate identification of victim rows without adding complexity to the primary memory access operations, as the counting occurs independently and concurrently.
Data Source
AI summary
A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.