Refresh Counter Circuit for DRAM Multi-Pulse Counting
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Solution Overview
Problem
Dynamic random access memory (DRAM) faces challenges with limited data retention due to charge leakage, requiring periodic refresh operations, where the reliability of the refresh counter in generating refresh pulse signals affects the success of these operations.
Innovation Solution
A refresh counter circuit and method that include a first signal generator for generating a carry signal from each refresh pulse, a second signal generator for generating a second carry signal from the last refresh pulse, and counters for signal inversion and counting, ensuring accurate counting of refresh commands and addresses in multi-pulse refresh modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh counter is used to generate refresh pulse signals in DRAM, then periodic refresh operations can be performed to maintain data retention, but the counter may fail to count reliably under certain conditions, affecting refresh operation success
Solution Approach 1:
The refresh counter is divided into multiple independent counters (first counter, second counter, third counter) that each handle specific counting tasks. The first counter counts refresh commands, the second counter counts refresh pulses, and the third counter provides verification. This segmentation allows each counter to operate independently and reliably without being affected by the same conditions that would cause a single counter to fail.
Solution Approach 2:
The invention implements a feedback mechanism where the output of one counter serves as input to another counter, and the results are cross-verified. The first counter's output feeds to the second counter, and the third counter verifies the counting results. This feedback loop ensures that if one counter fails to count reliably, the system can detect the error through the other counters and correct the issue.
2Measurement precision
If the refresh counter counts multiple refresh pulses per command, then accurate tracking of refresh operations is achieved, but counting errors may occur under specific conditions affecting data integrity
Solution Approach 1:
The system uses multiple counters with feedback loops to verify counting accuracy. The first counter counts refresh commands, the second counter counts refresh pulses generated from those commands, and the third counter verifies the relationship between them. This feedback mechanism ensures that if counting errors occur, they are detected and corrected before affecting data integrity.
Solution Approach 2:
The invention performs preliminary counting and verification before the refresh operation is completed. By using multiple counters to track and verify the count in advance, the system ensures accuracy is established before potential errors could compromise data integrity, allowing for error detection and correction proactively rather than reactively.
Data Source
AI summary
A refresh counter circuit, a refresh counting method and a semiconductor memory are provided. The refresh counter circuit includes: a first signal generator that is configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command; a second signal generator that is configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command; a first counter that is configured to perform signal inversion according to the first carry signal and generate a first output signal; and a second counter that is configured to count the refresh command according to the second carry signal and generate a second output signal; where the refresh command generates at least two refresh pulse signals.