Semiconductor Error Correction Circuit for Refresh-Time Data Repair
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Solution Overview
Problem
Semiconductor devices face increased error occurrence due to faster data transmission speeds, necessitating advanced error correction methods to ensure reliable data transmission and storage, particularly during refresh operations.
Innovation Solution
Incorporation of an error correction circuit within semiconductor devices to detect and correct errors during read and refresh operations, utilizing failure detection signals to activate specific word lines and store error-corrected data, and a refresh control circuit to manage address signals and perform read-modify-write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission speed is increased, then operation speed of semiconductor device is improved, but error occurrence probability increases
Solution Approach 1:
The patent applies preliminary action by performing error correction during refresh operations before errors can propagate. The system proactively detects and corrects errors in stored data by activating word lines, detecting errors through error correction circuits, and rewriting corrected data back to the same or different word lines, preventing future data transmission errors.
Solution Approach 2:
The patent implements feedback mechanisms where error correction circuits continuously monitor data integrity during refresh operations. When errors are detected, the system generates feedback signals to trigger corrective actions, including activating repair word lines and rewriting corrected data, thereby creating a closed-loop error prevention system that maintains reliability at high speeds.
2Reliability
If error correction operations are performed during refresh, then data reliability is improved, but operation complexity increases
Solution Approach 1:
The patent applies universality by designing the error correction circuit to perform multiple functions within the existing refresh operation framework. The same circuit infrastructure used for normal refresh operations is also utilized for error detection and correction, allowing the system to maintain data reliability without adding separate dedicated error correction hardware paths.
Solution Approach 2:
The patent implements self-service through automatic error correction mechanisms that operate autonomously during refresh cycles. The error correction circuits automatically detect errors, generate correction signals, and rewrite corrected data without requiring external intervention or complex control logic, thereby improving reliability while minimizing added complexity.
3Measurement precision
If failure address signals are stored and used during refresh, then error correction precision is improved, but control complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-storing failure address signals during write operations or initial system setup. These pre-stored addresses are then automatically retrieved and used during refresh operations to directly target and correct known problematic memory locations, improving error detection precision without requiring complex real-time analysis during refresh.
Solution Approach 2:
The patent implements copying by maintaining copies of failure address information in dedicated storage circuits. These copied address signals are readily available during refresh operations, allowing the error correction circuit to quickly identify and correct errors at specific word lines without regenerating address information, thereby improving precision while keeping control logic relatively simple.
Data Source
AI summary
An electronic device includes an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation, and a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored through as a failure address signal when the failure detection signal is input to the core circuit, and store the error-corrected internal data in the core circuit through a word line activated by the failure address signal during the refresh operation.