Memory Refresh Error Monitoring for Patrol-Read-Free ECC Correction
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Solution Overview
Problem
Volatile memory devices face issues with data loss due to charge leakage, leading to increased bit error rates and reduced yield, which existing error correction schemes struggle to address effectively, especially as manufacturing scales shrink.
Innovation Solution
A memory system and method that generates error information during refresh operations, allowing for error correction without patrol read operations, thereby reducing power consumption and enhancing reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If patrol read operations are performed for error detection and correction in volatile memory, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges the error detection function with the existing refresh operation by incorporating error detection circuitry that monitors memory cells during the refresh process. This combination allows error detection without requiring separate patrol read operations, thereby maintaining data reliability while reducing power consumption.
Solution Approach 2:
The refresh operation is enhanced to serve multiple functions: it not only recharges memory cell capacitors to prevent data loss but also performs error detection through integrated error detection circuitry. This multi-functionality eliminates the need for dedicated patrol read operations for error detection.
2Productivity
If manufacturing process scale is lowered to increase integration degree, then device integration is improved, but bit error rate increases
Solution Approach 1:
The patent implements error detection circuitry that continuously monitors memory cells during refresh operations and provides feedback about detected errors. This feedback mechanism enables real-time error detection and correction, compensating for the increased bit error rate caused by smaller manufacturing process scales and higher integration degrees.
Solution Approach 2:
The memory system performs self-diagnosis and self-correction by incorporating error detection and correction capabilities directly into the refresh operation. The system automatically detects and corrects errors without external intervention, maintaining reliability despite increased integration and smaller process scales.
Data Source
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AI summary
A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.