DRAM Refresh Testing Circuit Internal Signal Observation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory testing methods for DRAM require additional control circuits to test the refresh function, which alters the original control time sequence and prolongs the testing time, and do not allow internal triggering of the precharge operation.
Innovation Solution
A refresh testing circuit comprising an internal clock generator, counter, and address detection circuit that detects the refresh signal without changing the original control time sequence by generating a bank selection signal and row address signal, allowing the counter to count variations and the address detection circuit to verify sequential address increases, thereby determining the number of refresh operations and addresses without additional write or read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional control circuits are used to trigger precharge operation during refresh testing, then the refresh function can be tested, but the control time sequence changes and testing time increases
Solution Approach 1:
The refresh controller automatically triggers the precharge operation based on the row address signal reaching its maximum value, without requiring external control circuits. The testing circuit observes the natural operation of the refresh controller, allowing the precharge to be triggered internally during the test process, thus maintaining the original control time sequence and reducing testing time
Solution Approach 2:
The testing circuit introduces an intermediary observation mechanism that monitors the row address signal and bank selection signal without interfering with the normal refresh control flow. This intermediary detection approach allows testing to proceed without altering the original control time sequence, avoiding the need for additional control circuits that would prolong the test
2Reliability
If additional control circuits are used to trigger precharge operation, then the refresh function can be tested, but the control time sequence changes
Solution Approach 1:
The refresh controller's internal logic naturally triggers the precharge operation when the row address reaches its maximum value during refresh sequences. The testing circuit leverages this self-service capability by observing rather than controlling the precharge trigger, eliminating the need for additional external control circuits and maintaining simplicity
Solution Approach 2:
The testing function is extracted as a separate observation circuit that monitors the refresh controller's output signals without being integrated into the control path. This extraction allows the test circuit to detect refresh operations and precharge triggers independently, avoiding the need to add complex control circuits that would modify the original control logic
3Reliability
If write operations are performed to detect refreshed data, then the refresh function can be tested, but sufficient time for write operation cannot be obtained
Solution Approach 1:
The testing method replaces the mechanical write operation approach with an electrical signal observation approach. Instead of writing data and reading it back (which requires time-consuming memory operations), the circuit electronically monitors the refresh controller's output signals (row address and bank selection) to infer whether refresh operations occurred, providing instantaneous test results without occupying memory write time
Solution Approach 2:
An intermediary detection circuit is introduced that observes the relationship between the row address signal and bank selection signal to determine if refresh operations occurred. This intermediary observation method provides test information without requiring the time-consuming write and read operations, allowing the test to complete within the available refresh time window
Data Source
AI summary
A refresh testing circuit and method are provided. The refresh testing circuit includes an internal clock generator, a counter, and an address detection circuit. The internal clock generator transmits a control clock signal to a refresh controller to generate a bank selection signal and a row address signal for a refresh operation. The counter counts variations of the bank selection signal to generate a count value. The address detection circuit detects whether a value of the row address signal is sequentially increased during the refresh operations to generate a detection signal.