Refresh Time Detection Circuit for DRAM Stress Testing
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Solution Overview
Problem
Current methods for testing semiconductor devices, such as DRAMs, face challenges in detecting refresh time variations under stress temperature conditions, which can lead to inconsistent data retention and reduced product reliability due to inadequate detection of optimal stress temperature points.
Innovation Solution
A refresh time detection circuit is introduced, comprising a code generator, latch circuit, subtractor, and comparator, which generates and processes signals to detect refresh time variations by comparing pre-code and post-code signals with an offset signal, allowing for the identification of suitable stress temperature points and minimizing data retention time variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If burn-in test with high voltage and high temperature is applied to detect defective parts, then defective or failed parts can be discovered at early stage, but refresh time variations under stress temperature conditions cannot be precisely detected
Solution Approach 1:
The test process is segmented into distinct phases: pre-stress latching of code signals, stress application, post-stress latching, and comparison. This segmentation allows precise measurement of refresh time variations by capturing code signals at specific time points before and after stress, rather than using a monolithic burn-in test approach.
Solution Approach 2:
The invention implements a feedback mechanism where the detected refresh time variation is compared against a reference value to determine pass/fail status. The code generator continuously provides reference code signals, and the comparator provides feedback on whether the measured refresh time falls within acceptable parameters, enabling precise quality control.
2Ease of operation
If arbitrary operational conditions are applied through experimental data to pass cells, then DRAMs can operate, but optimal stress temperature points cannot be identified leading to inconsistent data retention
Solution Approach 1:
The invention systematically varies the stress temperature parameter to identify optimal operating conditions. By applying different temperature stresses and measuring the corresponding refresh time variations, the system can determine the optimal stress temperature point that ensures consistent data retention across all DRAM units, replacing arbitrary experimental conditions with scientifically determined parameters.
3Reliability
If excessive stress is applied during testing to ensure reliability, then defective parts are detected, but cell data retention characteristics vary due to unidentified saturation points
Solution Approach 1:
The invention performs preliminary latching of code signals before stress application and another latching after stress application. This preliminary action of capturing reference states enables precise measurement of changes in data retention characteristics, allowing identification of the saturation point where excessive stress begins to cause variability, thus optimizing the stress level for reliable testing.
Data Source
AI summary
A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.