Regenerative FET Gate Charging With Inductor Timing Control

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Solution Overview

Problem

Large field effect transistors (FETs) in synchronous switching power converters experience significant gate capacitance charging and discharging losses due to high switching frequencies, leading to inefficiencies in power conversion.

Innovation Solution

A circuit and method for regenerative gate charging using an inductor and controlled current manipulation, where an inductor is coupled to the gate of the FET, and a bridged inductor driver circuit with timing control circuits adjust switch timing profiles based on sampled gate voltages to optimize charging and discharging, reducing power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If switching frequency is increased to improve productivity, then power conversion efficiency improves, but gate capacitance power losses increase

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidgate capacitance power losses
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent establishes a continuous energy recycling loop where the gate capacitance discharge energy from one switching cycle is immediately captured and reused for the next charging cycle. This continuous regeneration process ensures that useful energy action persists across switching cycles, maintaining high productivity while reducing the net energy loss that would otherwise increase with higher switching frequencies.

Inventive Principle:
Principle #20Continuity of useful action

2Loss of energy

If regenerative charging is implemented to reduce power loss, then energy efficiency improves, but device complexity increases

Engineering Contradiction:
Improvepower lossVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the gate driver functionality with inductor-based energy storage and recovery circuits into a unified bridged inductor driver structure. By combining the charging path, discharging path, and energy recovery path into a single integrated circuit topology, the design achieves regenerative charging without requiring separate independent circuits for each function, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes power loss by recovering energy during switching cycles, enhancing the efficiency of power conversion in synchronous switching power converters.

Implementation Method 1

A low-side drive circuit is coupled to a gate of the low-side FET. The low-side drive circuit includes an inductor coupled to the gate of the low-side FET such that current flow through the inductor charges and discharges the gate of the low-side FET.

Methodology Applied
Scientific EffectElectromagnetic energy storage: Inductor

Data Source

PatentUS11996836B2Controlled current manipulation for regenerative charging of gate capacitance
Publication Date: 2024.05.28 SILANNA ASIA
  • US11996836B2 patent drawing
  • US11996836B2 patent drawing
  • US11996836B2 patent drawing

AI summary

A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.