Regular Expression Engine With Multi-Port RAM and Load Balancing
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Solution Overview
Problem
Central Processing Units (CPUs) lack the processing power and bandwidth to perform regular expression processing in real time, leading to insufficient data throughput for responsive matching operations.
Innovation Solution
A circuit-based regular expression processing system utilizing a multi-port RAM and a hardware finite state automata (HFA) graph to efficiently process data streams, with a decoder circuit and switching circuitry for load balancing and path prioritization, allowing for concurrent processing of active states and priority-based routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CPU is used to execute regular expression processing, then the system is simple and flexible, but the data throughput is insufficient (100-200 Mbps) and real-time processing capability is lacking
Solution Approach 1:
The patent replaces the mechanical software-based CPU execution model with a hardware-based regular expression processing engine that uses circuit-level parallelism and state machine architecture to achieve real-time pattern matching at line rates, eliminating the throughput bottleneck of software interpretation
Solution Approach 2:
The processing engine is segmented into multiple independent state machines and processing pipelines that can concurrently evaluate different regular expressions and data streams, with each segment handling specific pattern matching tasks to distribute the processing load and increase overall throughput
2Adaptability or versatility
If multiple active states are tracked concurrently to support complex regular expressions, then the processing capability is improved, but the memory access complexity and resource consumption increase
Solution Approach 1:
The patent transitions from sequential memory access to parallel multi-port memory access, adding the dimension of concurrent read/write operations. Multiple state memories can simultaneously access the instruction table without conflict, enabling complex regular expression processing while maintaining constant memory access time regardless of the number of active states
3Productivity
If load balancing technique is used to route active states to multiple memories, then the processing throughput is improved, but the switching control complexity increases
Solution Approach 1:
The switching circuitry automatically performs load balancing by monitoring the state of multiple memories and dynamically routing active states to the least-loaded memory, eliminating the need for external controller intervention and reducing switching control complexity while maintaining optimal throughput
Data Source
AI summary
A system includes a multi-port random-access memory (RAM) configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine configured to process the data stream based on the instruction table. The regular expression engine includes a decoder circuit configured to determine validity of active states output from the RAM, a plurality of active states memories operating concurrently, wherein each active states memory is configured to initiate a read from a different port of the RAM using an address formed of an active state output from the active states memory and a portion of the data stream, and switching circuitry configured to route the active states to the plurality of active states memories according, at least in part, to a load balancing technique and validity of the active states.