Regular Expression Engine with Priority Path Routing
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Solution Overview
Problem
Central Processing Units (CPUs) lack the processing power and bandwidth to perform regular expression processing in real time, leading to insufficient data throughput for responsive matching in various industries.
Innovation Solution
A circuit-based regular expression processing system utilizing a multi-port RAM and a hardware finite state automata (HFA) graph to efficiently process data streams, with a decoder circuit and switching circuitry for load balancing and path prioritization, allowing for concurrent processing of active states and priority-based routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CPU is used to execute regular expression processing, then the system is simple and flexible, but the data throughput is insufficient (100-200 Mbps) and cannot provide real-time responsive processing
Solution Approach 1:
The patent replaces the software-based CPU execution model with a hardware-based finite state automata processing system. The regular expression engine is implemented as dedicated hardware circuitry with state machines that process data streams in parallel, achieving deterministic finite automata (DFA) performance in hardware rather than software. This substitution of mechanical/software processing with hardware processing fundamentally increases throughput while maintaining the regular expression processing function.
Solution Approach 2:
The patent segments the regular expression processing into multiple parallel finite state automata instances, each handling specific regular expressions. The system divides the data stream processing into concurrent operations across multiple state machines, allowing simultaneous processing of multiple patterns. This segmentation enables the system to handle many regular expressions in parallel, dramatically increasing overall throughput beyond what a single CPU thread could achieve.
2Adaptability or versatility
If multiple active states are tracked concurrently for complex regular expressions, then the matching capability is improved, but the memory access complexity and processing overhead increase
Solution Approach 1:
The patent merges multiple active state tracking operations into a unified hardware state machine architecture. Instead of separately managing memory accesses for each active state, the system combines state transitions, memory reads, and writes into integrated hardware pathways. The finite state automata are designed to track multiple active states simultaneously through shared hardware resources, reducing the overall complexity of memory access control while maintaining the ability to handle complex regular expressions with many active states.
Solution Approach 2:
The patent performs preliminary compilation of regular expressions into deterministic finite automata (DFA) representations before runtime processing. During compilation, the system pre-calculates state transitions, optimizes memory access patterns, and generates efficient instruction sequences. This preliminary action transforms complex regular expressions into optimized hardware-friendly formats, reducing the complexity of runtime memory access and state management while preserving full matching capability.
Data Source
AI summary
A system includes a multi-port RAM configured to store an instruction table. The instruction table specifies a regular expression for application to a data stream. The system includes a regular expression engine (engine) that processes the data stream using the instruction table. The engine includes a decoder circuit that determines validity of active states output from the multi-port RAM and a plurality of priority FIFO memories (PFIFOs) operating concurrently. Each PFIFO can initiate a read from a different port of the multi-port RAM. Each PFIFO can track a plurality of active paths for the regular expression and a priority of each active path by, at least in part, storing entries corresponding to active states in each respective PFIFO in decreasing priority order. The engine includes switching circuitry that selectively routes the active states from the decoder circuit to the plurality of PFIFOs according to the priority order.