Region-Based Error Detection in Integrated Circuit Configuration Memory
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Solution Overview
Problem
Programmable logic devices face frequent reboots due to single event upsets (SEUs) and tampering, which affect the operation and performance, especially as CRAM cell densities increase, leading to undesirable performance impacts across numerous devices.
Innovation Solution
A floorplan of regions in an integrated circuit and a physical representation of CRAM address lookup are used to rapidly identify and classify errors, allowing for targeted error correction without rebooting, by determining the physical location of errors and performing corrective operations based on the location in the floorplan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CRAM cell density is increased, then device functionality and integration are improved, but SEU frequency increases leading to more reboots
Solution Approach 1:
The patent segments the CRAM memory into multiple regions (first region, second region, third region) with different error correction characteristics. Each region can be independently managed and corrected, allowing the system to maintain high density while reducing overall SEU impact through localized correction strategies.
Solution Approach 2:
Different regions of the CRAM memory are assigned different error correction policies based on their criticality and error rates. The patent applies local quality by implementing region-specific correction mechanisms rather than uniform correction across all memory, optimizing reliability without sacrificing density.
2Reliability
If rebooting is used to correct errors, then error correction is achieved, but performance impact and time loss increase
Solution Approach 1:
The patent implements preliminary action by continuously monitoring CRAM regions and performing error correction before reboots are necessary. The system proactively identifies and corrects errors in non-critical regions, preventing the need for time-consuming reboot operations and maintaining continuous device performance.
Solution Approach 2:
Instead of performing full system reboots to correct all errors, the patent applies partial correction by targeting only specific affected regions. This partial action approach corrects errors without requiring complete system restart, significantly reducing time loss while maintaining reliability.
3Productivity
If region-based error management is implemented, then error correction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by creating a multi-functional error management system that handles multiple error types (SEUs, tampering) and regions through a unified architecture. The same regional classification framework serves both error detection and correction functions, improving efficiency without proportionally increasing complexity.
Data Source
AI summary
Systems and methods for detecting and managing errors in integrated circuits are provided. In one example, a system includes an integrated circuit that includes configuration memory that defines a circuit design implemented by the integrated circuit. The circuit design includes a plurality of regions. Additionally, the system is configured to determine a physical location of an error in the configuration memory and determine a location in a floorplan of the configuration memory that corresponds to the physical location of the error in the configuration memory. The floorplan identifies where the plurality of regions are defined in the configuration memory. The system is configured to determine in which of the plurality of regions the error in the configuration memory has occurred based at least in part on the location in the floorplan. Also, the system is configured to perform a corrective operation based on the location in the floorplan.