Network-on-Chip Region Routing Tables for Deadlock-Free Paths
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Solution Overview
Problem
Existing Network-on-Chip routing methods face inefficiencies due to high runtime and memory consumption from exhaustive route exploration, and they often fail to address network deadlocks, especially in conventional Network-on-Chip architectures.
Innovation Solution
A region-based method for generating a deadlock-free routing table that predicts the shortest path using user-input constraints such as throughput, latency, and router-turns, splitting source-destination pairs, and performing deadlock analysis to reroute if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If exhaustive route exploration is used to find the shortest path, then routing accuracy is improved, but runtime consumption increases significantly
Solution Approach 1:
The patent divides the network graph into multiple regions based on source and destination coordinates. Instead of exploring all possible routes in the entire graph, the algorithm segments the search space into relevant regions, significantly reducing the number of nodes that need to be visited while maintaining routing accuracy.
Solution Approach 2:
The patent performs preliminary actions by predicting the shortest path distance and identifying possible regions before actually finding the shortest path. This preliminary region identification step prunes the search space in advance, preventing exhaustive exploration of irrelevant areas and reducing runtime consumption.
2Measurement precision
If exhaustive route exploration is used to find the shortest path, then routing accuracy is improved, but memory consumption increases significantly
Solution Approach 1:
The patent segments the network into multiple regions and processes each region separately. This segmentation reduces the memory footprint by only storing and processing relevant path information for current regions being explored, rather than maintaining data structures for the entire network graph.
Solution Approach 2:
By predicting possible regions in advance before pathfinding, the algorithm prepares a limited set of candidate regions that need to be stored in memory. This preliminary action prevents the need to allocate memory for exploring all possible routes throughout the entire network.
3Device complexity
If conventional shortest path algorithms are used, then path finding is simplified, but network deadlocks cannot be addressed
Solution Approach 1:
The patent incorporates feedback mechanisms by performing deadlock analysis on the generated routing table. The system checks for potential deadlocks and adjusts routing paths accordingly, creating a feedback loop that ensures deadlock freedom while maintaining reasonable algorithm complexity.
Solution Approach 2:
The patent performs preliminary deadlock analysis during the routing table generation process. By identifying and preventing deadlocks in advance rather than handling them during runtime, the algorithm maintains simplicity while ensuring reliability through proactive deadlock detection and prevention.
Data Source
AI summary
The present invention relates to a computer-implemented method of generating a Network-on-Chip routing table, said method comprising the steps of: identifying source and destination by coordinates; sorting source-destination list based on user-input constraints; iterating source-destination pairs in the sorted source-destination list to find a shortest routing path from the source to the destination; splitting each source-destination pair to multiple sub source-destination pairs based on one of the user-input constraints; iterating each of the sub source-destination pairs to find a shortest routing path in a sub source-destination list; creating routing table for each sub source-destination pair based on the user-input constraints; combining the routing tables of sub source-destination pairs to generate a source-destination pairs routing table; performing routing table deadlock detection before proceeding to generate a routing table for next source-destination pair; wherein the user-input constraints comprising desired throughputs, desired latency, number of router-turns and region restriction for routing; and wherein performing deadlock analysis and rerouting the source-destination pair if deadlock is detected.