Region-Based Cache Directory for Large-Cache Coherency

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Solution Overview

Problem

Maintaining cache coherency in multi-node computer systems with large cache sizes is challenging due to the linear increase in cache directory size, making it difficult to efficiently track cache lines and manage coherency protocols.

Innovation Solution

Implementing a region-based cache directory that tracks cache lines on a region basis, using reference counts and arrays at different granularities to reduce directory size and optimize probe generation, with mechanisms to transition between region and line tracking based on access patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a line-based cache directory scheme is used to track each cache line individually, then cache coherency can be maintained accurately, but the cache directory size increases linearly with total cache capacity

Engineering Contradiction:
Improvecache coherency tracking accuracyVSAvoidcache directory size
Core Design Contradiction:
ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent divides the cache directory into multiple segments or tables, each tracking a subset of cache lines. Instead of a single large directory tracking all cache lines, the system uses multiple smaller directories organized in a hierarchical or distributed manner, reducing the size of any individual directory structure while maintaining comprehensive tracking capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an additional dimension to cache line tracking by organizing directories hierarchically across multiple levels (e.g., L1, L2, L3 cache levels) or by adding spatial distribution across multiple nodes. This dimensional organization allows the system to track cache lines efficiently without requiring a single linearly scaling directory structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If cache directory size is reduced to manage large caches efficiently, then memory bandwidth is improved, but the ability to track individual cache lines for coherency protocols deteriorates

Engineering Contradiction:
Improvememory bandwidthVSAvoidcache line tracking capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces intermediary structures such as index tables, mapping structures, or proxy directories that mediate between the reduced-size directory and the actual cache lines. These intermediaries enable the system to track cache lines indirectly through compact representations, maintaining coherency information without requiring full-size directory entries for each cache line.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses compact copies or representations of cache line information stored in the directory, rather than full cache line metadata. By storing compressed, encoded, or selective copies of coherency information (such as validity bits, ownership status, or set identifiers), the system maintains tracking capability with reduced directory size.

Inventive Principle:
Principle #26Copying

3Productivity

If probe bandwidth is reduced by optimizing directory structure, then system scalability is improved, but the precision of coherency state detection may be compromised

Engineering Contradiction:
Improveprobe bandwidth efficiencyVSAvoidcoherency state detection accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary organization and pre-computation of coherency information in the directory structure, such as pre-calculating probe targets, pre-organizing cache line groupings, or pre-establishing mapping relationships. This preliminary action enables the system to process probe requests more efficiently with reduced bandwidth requirements while maintaining accurate coherency state detection through pre-validated data structures.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4293521B1Region based directory scheme to adapt to large cache sizes
Publication Date: 2025.10.15 ADVANCED MICRO DEVICES INC
  • EP4293521B1 patent drawingFigure 1
  • EP4293521B1 patent drawingFigure 2
  • EP4293521B1 patent drawingFigure 3

AI summary

Systems, apparatuses, and methods for maintaining a region-based cache directory are disclosed. A system includes multiple processing nodes, with each processing node including a cache subsystem. The system also includes a cache directory to help manage cache coherency among the different cache subsystems of the system. In order to reduce the number of entries in the cache directory, the cache directory tracks coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Accordingly, the system includes a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system. The cache directory includes a reference count in each entry to track the aggregate number of cache lines that are cached per region. If a reference count of a given entry goes to zero, the cache directory reclaims the given entry.