Semiconductor Memory Structure With Region-Specific Gate Widths
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Solution Overview
Problem
Existing semiconductor memory devices, particularly one-time programmable (OTP) NVM devices, suffer from degraded cell current due to increased gate resistance leading to parasitic voltage drops and device failures, which are not adequately addressed by current fabrication techniques.
Innovation Solution
The fabrication method involves forming gate structures with different gate lengths by selectively recessing gate spacers in the BEOL process to create distinct gate structures with varying widths, ensuring optimal performance by minimizing gate leakage current and preventing punch-through, thereby enhancing device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate resistance is increased to improve programming capability, then programming capability is improved, but cell current degrades due to parasitic voltage drops
Solution Approach 1:
The patent applies local quality by creating different gate structure configurations in different regions of the memory device. Specifically, it forms first gate structures with first gate lengths in first regions and second gate structures with second gate lengths in second regions, where the gate lengths are differentiated to optimize local electrical characteristics. This allows different areas of the device to have tailored gate resistance and leakage characteristics, resolving the contradiction between programming capability and cell current maintenance.
Solution Approach 2:
The patent changes the gate length parameter to resolve the technical contradiction. By forming gate structures with different gate lengths (first gate length vs. second gate length) in different regions, the invention optimizes the balance between gate resistance for programming and leakage current for reliability. This parameter variation allows simultaneous optimization of both conflicting requirements.
2Object-generated harmful factors
If gate length is reduced to decrease gate leakage current, then gate leakage current is reduced, but punch-through risk increases
Solution Approach 1:
The patent applies local quality by creating different gate structure configurations in different regions of the memory device. Specifically, it forms first gate structures with first gate lengths in first regions and second gate structures with second gate lengths in second regions, where the gate lengths are differentiated to optimize local electrical characteristics. This allows different areas of the device to have tailored gate resistance and leakage characteristics, resolving the contradiction between programming capability and cell current maintenance.
Solution Approach 2:
The patent makes the gate structure dynamic by allowing different gate lengths in different regions rather than using a uniform gate length throughout. This dynamic configuration enables the device to adapt gate characteristics to local requirements, reducing leakage where possible while maintaining punch-through protection where needed.
Data Source
AI summary
A semiconductor structure includes a first channel region and a second channel region, a first gate structure over the first channel region and a second gate structure over the second channel region, first gate spacers disposed on sidewalls of the first gate structure and over the first channel region, and second gate spacers disposed on sidewalls of the second gate structure and over the second channel region. The first gate structure has a first width, and the second gate structure has a second width greater than the first width. The first gate spacers each have a third width, and the second gate spacers each have a fourth width less than the third width. The first and the second gate structure each extend lengthwise in a first direction. The first width, the second width, the third width, and the fourth width are in a second direction perpendicular to the first direction.