Region-Specific Memory Access Scheduling for Stacked-Die Arrays
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Solution Overview
Problem
Conventional memory systems manage performance variations by using conservative timing parameters based on worst-case scenarios, leading to inefficiencies in memory access scheduling due to region-to-region variations in memory cell access times and signal propagation delays, particularly in stacked-die memory architectures.
Innovation Solution
Implementing a memory controller that profiles and stores region-specific memory timing parameters for each region of the memory array, allowing for optimized scheduling of memory accesses based on these variations, thereby reducing latency and improving bandwidth and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative worst-case timing parameters are used for memory access scheduling, then reliability is improved, but productivity deteriorates
Solution Approach 1:
The memory array is divided into multiple regions, and timing parameters are profiled and stored separately for each region. The memory controller schedules accesses to different regions using region-specific timing parameters rather than a single worst-case parameter set, enabling optimized memory access scheduling that improves productivity while maintaining reliability through region-appropriate timing.
Solution Approach 2:
Different timing parameters are applied to different memory regions based on their specific performance characteristics. The system profiles timing parameters for each region and uses the appropriate regional parameters for scheduling, rather than applying a uniform worst-case parameter set across the entire memory array, thus improving overall memory access efficiency.
2Productivity
If region-specific timing parameters are profiled and stored, then productivity is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary profiling of timing parameters for each memory region during manufacturing or initialization, and stores these parameters in advance. This preliminary action eliminates the need for complex real-time analysis during operation, as the memory controller can directly use the pre-profiled regional parameters for scheduling decisions, thereby improving productivity without excessive operational complexity.
Data Source
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AI summary
An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.